From 7742e7756c0637ae5378e394ca03978826e31a78 Mon Sep 17 00:00:00 2001 From: Rahul Prabhakar Date: Tue, 13 Sep 2011 15:40:45 -0700 Subject: ARM: tegra: TrustedLogic drop 32055 The WARs checked into 12r7: disable LP0/LP1 and slave LP2, and force maxcpus to 1 aren't needed when used with the newer tf_include.h from this TL drop. bug 868906 bug 870224 bug 877339 Change-Id: Ic3002b1d5fa09e8171c0d43bf6978ae96e51daf8 Reviewed-on: http://git-master/r/53324 Reviewed-by: Rahul Prabhakar Tested-by: Rahul Prabhakar Reviewed-by: Niket Sirsi Reviewed-by: Jonathan White --- arch/arm/mach-tegra/cortex-a9.S | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-tegra/cortex-a9.S') diff --git a/arch/arm/mach-tegra/cortex-a9.S b/arch/arm/mach-tegra/cortex-a9.S index 96f915725eb1..da571910ca06 100644 --- a/arch/arm/mach-tegra/cortex-a9.S +++ b/arch/arm/mach-tegra/cortex-a9.S @@ -465,6 +465,12 @@ ENTRY(__cortex_a9_restore) mcr p15, 2, r0, c0, c0, 0 @ csselr mcr p15, 0, r1, c1, c0, 0 @ sctlr +#ifndef CONFIG_TRUSTED_FOUNDATIONS + /* + * Restoring ACTRL / PCTLR needs to be done by secure code + * as not all bits of ACTRL are writable (and none of PCTLR) + * by non-secure code. + */ tst r2, #(0x1 << 6) orrne r2, r2, #(1 << 0) @ sync FW bit with SMP state mcr p15, 0, r2, c1, c0, 1 @ actlr @@ -475,8 +481,6 @@ ENTRY(__cortex_a9_restore) orreq r3, r3, #(3<<8) @ set MAXCLKLATENCY to 3 on G orrne r3, r3, #(2<<8) @ set MAXCLKLATENCY to 2 on LP #endif -#ifndef CONFIG_TRUSTED_FOUNDATIONS - //TL : moved to secure mcr p15, 0, r3, c15, c0, 0 @ pctlr #endif -- cgit v1.2.3