From 98e66926adcf7af88c87f467a11fba35c143f663 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Mon, 30 Jan 2012 13:42:05 -0800 Subject: ARM: tegra: power: Separate lp2 latency for G/LP CPU modes Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes. Separately measure and adjust latency in each mode; restart calculation after mode switch from the last measured latency in the target mode. Reviewed-on: http://git-master/r/78344 Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f Signed-off-by: Alex Frid Signed-off-by: Varun Wadekar Reviewed-on: http://git-master/r/78902 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- arch/arm/mach-tegra/cpuidle.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm/mach-tegra/cpuidle.h') diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h index 12a29ff2e236..ce6eab940fd8 100644 --- a/arch/arm/mach-tegra/cpuidle.h +++ b/arch/arm/mach-tegra/cpuidle.h @@ -98,6 +98,16 @@ static inline bool tegra_lp2_is_allowed(struct cpuidle_device *dev, #endif } +static inline void tegra_lp2_set_global_latency(struct cpuidle_state *state) +{ +#ifdef CONFIG_ARCH_TEGRA_2x_SOC + state->exit_latency = tegra_lp2_exit_latency; +#endif + /* Tegra3 does not use global exit latency */ +} + +void tegra_lp2_update_target_residency(struct cpuidle_state *state); + #ifdef CONFIG_DEBUG_FS static inline int tegra_lp2_debug_show(struct seq_file *s, void *data) { -- cgit v1.2.3