From ab7b7f907c9b7ae9812581ff5535fd98474ba76b Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 5 Mar 2010 19:08:02 -0800 Subject: Tegra RM: Removed 50MHz floor for MIPI PLL output. Removed 50MHz floor for MIPI PLL high speed output frequency. This floor kept MIPI PLL low speed output (= high speed output / 8) above DSI panel specification - bug 651446. Change-Id: Id1d3314b46896cc8f6fb48d238ffed01fd6b4e4a Reviewed-on: http://git-master/r/787 Tested-by: Aleksandr Frid Reviewed-by: Venkata (Muni) Anda Tested-by: Venkata (Muni) Anda --- arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c') diff --git a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c index d19a99b3f08b..36dd76c92086 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c +++ b/arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_clock_config.c @@ -647,6 +647,13 @@ NvRmPrivAp15PllConfigureSimple( { // PLLD output is always divided by 2 (after P-divider) VcoKHz = VcoKHz << 1; MaxOutKHz = MaxOutKHz << 1; + while (VcoKHz < pCinfo->PllVcoMin) + { + VcoKHz = VcoKHz << 1; + MaxOutKHz = MaxOutKHz << 1; + P++; + } + NV_ASSERT(P <= CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK); flags = NvRmPllConfigFlags_DiffClkEnable; } if (pCinfo->SourceId == NvRmClockSource_PllX0) @@ -1052,13 +1059,6 @@ Ap15PllDConfigure( else { // for other targets use simple variable configuration - if (TargetFreq < NVRM_PLLD_DISPLAY_MIN_KHZ) - { - NV_ASSERT((TargetFreq * NVRM_DISPLAY_DIVIDER_MAX) >= - NVRM_PLLD_DISPLAY_MIN_KHZ); - TargetFreq = - ((NVRM_PLLD_DISPLAY_MIN_KHZ / TargetFreq) + 1) * TargetFreq; - } NV_ASSERT(TargetFreq <= MaxFreq); NvRmPrivAp15PllConfigureSimple( hRmDevice, NvRmClockSource_PllD0, MaxFreq, &TargetFreq); -- cgit v1.2.3