From 5dc76d854da2b2952480f2c067d5d5e815a925d1 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Thu, 13 Mar 2014 14:40:01 -0700 Subject: ARM: tegra12: dvfs: Set CPU rate limit to 2.2GHz Set CPU rate limit to 2.2GHz for Tegra12 sku 0x27. Bug 1475295 Change-Id: Ia96011bf398dfb35721b201bd799ea66e9cdf78e Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/381750 (cherry-picked from commit f703fdc9373905a82437f673ab557c32ac63c59c) Reviewed-on: http://git-master/r/384840 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu --- arch/arm/mach-tegra/tegra12_edp.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-tegra/tegra12_edp.c') diff --git a/arch/arm/mach-tegra/tegra12_edp.c b/arch/arm/mach-tegra/tegra12_edp.c index d0c3455545fa..84f026618ce1 100644 --- a/arch/arm/mach-tegra/tegra12_edp.c +++ b/arch/arm/mach-tegra/tegra12_edp.c @@ -204,6 +204,7 @@ struct tegra_sysedp_corecap *tegra_get_sysedp_corecap(unsigned int *sz) gpu_speedo_id = tegra_gpu_speedo_id(); switch (cpu_speedo_id) { + case 0x5: case 0x2: if (gpu_speedo_id == 1) { /* 575 variants */ @@ -316,6 +317,10 @@ static struct tegra_edp_cpu_leakage_params t12x_leakage_params[] = { .cpu_speedo_id = 3, /* Prod SKU */ EDP_PARAMS_COMMON_PART, }, + { + .cpu_speedo_id = 5, /* Prod SKU */ + EDP_PARAMS_COMMON_PART, + }, }; #ifdef CONFIG_TEGRA_GPU_EDP -- cgit v1.2.3