From d89936edd10c1b3acae86d1fe699aa66c1398fb3 Mon Sep 17 00:00:00 2001 From: vdumpa Date: Wed, 17 Nov 2010 15:57:13 -0800 Subject: tegra:arm: Set inner-WBWA/outer-WBNWA cacheability attributes Change the cacheability attributes in the normal memory remap register (NMRR) to inner write-back write-allocate/outer write-back no-write-allocate to improve L2 cache performance. Bug 728231 Bug 751146 Original-Change-Id: I992dd20b3cec3b0141ae114d5ae278122be0212d Reviewed-on: http://git-master/r/11077 Reviewed-by: Krishna Reddy Tested-by: Krishna Reddy Reviewed-by: Yu-Huan Hsu Reviewed-on: http://git-master/r/17475 Tested-by: Scott Williams Reviewed-by: Scott Williams Original-Change-Id: I0de3100975c592fe4a18780c2b0eb2c5d12258d7 Rebase-Id: R430708cbf798ff30f5a5394a5235942e95bda2d4 --- arch/arm/mm/proc-v7.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mm') diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index bfea95af079f..3ffe4c5da864 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -213,7 +213,7 @@ ENDPROC(cpu_v7_set_pte_ext) * NOS = PRRR[24+n] = 1 - not outer shareable */ .equ PRRR, 0xff0a89a8 -.equ NMRR, 0x40e044e0 +.equ NMRR, 0xc0e044e0 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ .globl cpu_v7_suspend_size -- cgit v1.2.3