From efe491be15ead3bbcf7e715337fdee7dfa41f699 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 11 Dec 2012 15:32:19 +0800 Subject: ENGR00216076-1: PM: Add Power Management driver for Vybrid System could run into STOP and LPRun modes. When system was working in STOP mode, pressing SW1 button or inserting or removing SD card could wake up it. Signed-off-by: Alison Wang --- arch/arm/plat-mxc/include/mach/mvf.h | 17 +++++++++++------ arch/arm/plat-mxc/include/mach/mxc.h | 14 ++++++++++++++ 2 files changed, 25 insertions(+), 6 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index 9ef4de35d4c0..1e3f74f98857 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -53,8 +53,7 @@ * IRAM */ #define MVF_IRAM_BASE_ADDR 0x3F000000 /* internal ram */ -#define MVF_IRAM_PARTITIONS 2 -#define MVF_IRAM_SIZE (MVF_IRAM_PARTITIONS * SZ_256K) /* 512KB */ +#define MVF_IRAM_SIZE (SZ_256K) /* 256KB */ #ifdef CONFIG_MXC_VPU_IRAM @@ -169,12 +168,12 @@ #define MVF_EWM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00065000) #define MVF_I2C0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00066000) #define MVF_I2C1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00067000) -#define MVF_WKUP_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006A000) +#define MVF_WKPU_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006A000) #define MVF_CCM_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006B000) -#define MVF_GPC_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006C000) -#define MVF_VREG_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006D000) -#define MVF_SRC_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006E000) +#define MVF_GPC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006C000) +#define MVF_VREG_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006D000) +#define MVF_SRC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006E000) #define MVF_CMU_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006F000) #define L2_BASE_ADDR MVF_L2C_BASE_ADDR @@ -283,6 +282,12 @@ #define MVF_PGC_GPU_PGCR (MVF_PGC_GPU_BASE + 0x0) #define MVF_PGC_GPU_PGSR (MVF_PGC_GPU_BASE + 0xC) +/* Voltage Regulators */ +#define MVF_VREG_BASE (MVF_IO_ADDRESS(MVF_VREG_BASE_ADDR)) + +/* WKPU */ +#define MVF_WKPU_BASE (MVF_IO_ADDRESS(MVF_WKPU_BASE_ADDR)) + /* * defines for SPBA modules */ diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index afcf1255150b..b291d9015025 100755 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -257,6 +257,15 @@ struct cpu_op { u32 cpu_podf; }; +#ifdef CONFIG_SOC_MVFA5 +enum mvf_cpu_pwr_mode { + RUN_MODE, + LOW_POWER_RUN, + WAIT_MODE, + STOP_MODE, + LOW_POWER_STOP, +}; +#else enum mxc_cpu_pwr_mode { WAIT_CLOCKED, /* wfi only */ WAIT_UNCLOCKED, /* WAIT */ @@ -265,10 +274,15 @@ enum mxc_cpu_pwr_mode { STOP_POWER_OFF, /* STOP + SRPG */ ARM_POWER_OFF, /* STOP + SRPG + ARM power off */ }; +#endif int tzic_enable_wake(int is_idle); +#ifdef CONFIG_SOC_MVFA5 +extern void mvf_cpu_lp_set(enum mvf_cpu_pwr_mode mode); +#else extern void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode); +#endif extern int tzic_enable_wake(int is_idle); #endif -- cgit v1.2.3 From 97bb163197f3dc3405af90b5159e0f6b8a302586 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 11 Dec 2012 15:36:08 +0800 Subject: ENGR00216076-2: DCU: Update DCU driver for PM and blending issue Fix layers blending and reinitialization issue for DCU driver. Update power management part for DCU driver. Signed-off-by: Alison Wang --- arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h | 52 +---------------------------- 1 file changed, 1 insertion(+), 51 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h b/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h index b9d8dd3b93bb..9a5ba8e396a9 100644 --- a/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h +++ b/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h @@ -14,6 +14,7 @@ #define __MVF_DCU_FB_H__ #include +#include struct mvf_dcu_platform_data { char *mode_str; @@ -21,11 +22,6 @@ struct mvf_dcu_platform_data { int (*init) (int); }; -struct mfb_alpha { - int enable; - int alpha; -}; - struct dfb_chroma_key { int enable; __u8 red_max; @@ -36,60 +32,14 @@ struct dfb_chroma_key { __u8 blue_min; }; -struct layer_display_offset { - int x_layer_d; - int y_layer_d; -}; - #define DCU_LCD_ENABLE_PIN 30 #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key) #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8) -#define MFB_SET_ALPHA 0x80014d00 -#define MFB_GET_ALPHA 0x40014d00 -#define MFB_SET_LAYER 0x80084d04 -#define MFB_GET_LAYER 0x40084d04 - -#define FBIOGET_GWINFO 0x46E0 -#define FBIOPUT_GWINFO 0x46E1 - #ifdef __KERNEL__ #include -/* - * These are the fields of control descriptor for every layer - */ -struct dcu_layer_desc { - u32 layer_num; - u32 width; - u32 height; - u32 posx; - u32 posy; - u32 addr; - u32 blend; - u32 chroma_key_en; - u32 lut_offset; - u32 rle_en; - u32 bpp; - u32 trans; - u32 safety_en; - u32 data_sel_clut; - u32 tile_en; - u32 en; - u32 ck_r_min; - u32 ck_r_max; - u32 ck_g_min; - u32 ck_g_max; - u32 ck_b_min; - u32 ck_b_max; - u32 tile_width; - u32 tile_height; - u32 trans_fgcolor; - u32 trans_bgcolor; -} __packed; - - /* DCU registers */ #define DCU_CTRLDESCCURSOR1 0x0000 #define DCU_CTRLDESCCURSOR1_HEIGHT(x) (x << 16) -- cgit v1.2.3 From 3664f4e8ca3d18e87bc695f4b6838be61382dc17 Mon Sep 17 00:00:00 2001 From: Wang Xiaojun Date: Mon, 10 Dec 2012 18:35:41 +0800 Subject: ENGR00181365-1: ADC: Add platform support for ADC driver Add platform support for ADC driver. Signed-off-by: Wang Xiaojun --- arch/arm/plat-mxc/include/mach/devices-common.h | 9 +++++++++ arch/arm/plat-mxc/include/mach/mvf.h | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index a8a8034c1010..3cdcceaea09f 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -89,6 +89,15 @@ struct imx_imx2_wdt_data { struct platform_device *__init imx_add_imx2_wdt( const struct imx_imx2_wdt_data *data); +struct mvf_adc_data { + int id; + resource_size_t iobase; + resource_size_t iosize; + resource_size_t irq; +}; +struct platform_device *__init mvf_add_adcdev( + const struct mvf_adc_data *data); + struct imx_imxdi_rtc_data { resource_size_t iobase; resource_size_t irq; diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index 1e3f74f98857..6512c4e2bac6 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -145,7 +145,7 @@ #define MVF_PIT_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00037000) #define MVF_FTM0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00038000) #define MVF_FTM1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00039000) -#define MVF_ADC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003B000) +#define MVF_ADC0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003B000) #define MVF_TCON0_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003D000) #define MVF_WDOG1_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0003E000) #define MVF_LPTMR_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x00040000) -- cgit v1.2.3 From da9fd56e1e47c7773c8dfc4db445e3d1852d5aa5 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Tue, 11 Dec 2012 18:25:40 +0800 Subject: Vybrid CAAM driver From Singh Pradip-B09147. Integrate by Jason Jin Signed-off-by: Jason Jin --- arch/arm/plat-mxc/include/mach/devices-common.h | 17 +++++++++++++++++ arch/arm/plat-mxc/include/mach/mvf.h | 16 +++++++++++----- 2 files changed, 28 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h index 3cdcceaea09f..0e2a2a1d13e9 100755 --- a/arch/arm/plat-mxc/include/mach/devices-common.h +++ b/arch/arm/plat-mxc/include/mach/devices-common.h @@ -681,3 +681,20 @@ struct imx_rngb_data { struct platform_device *__init imx_add_rngb( const struct imx_rngb_data *data); + +struct mvf_caam_jr_data { + resource_size_t offset_jr; + resource_size_t irq_jr; +}; + +struct mvf_caam_data { + resource_size_t iobase_caam; /* entirety of CAAM register map */ + resource_size_t iobase_caam_sm; /* base of secure memory */ + resource_size_t iobase_snvs; /* base of SNVS */ + resource_size_t irq_sec_vio; /* SNVS security violation */ + resource_size_t irq_snvs; /* SNVS consolidated (incl. RTC) */ + struct mvf_caam_jr_data jr[4]; /* offset+IRQ for each possible ring */ +}; + +struct platform_device *__init mvf_add_caam( + const struct mvf_caam_data *data); diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index 6512c4e2bac6..838eef400e95 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -176,6 +176,11 @@ #define MVF_SRC_BASE_ADDR (MVF_AIPS0_BASE_ADDR + 0x0006E000) #define MVF_CMU_BASE_ADDR (MVF_AIPS1_BASE_ADDR + 0x0006F000) +#define MVF_CAAM_SECMEM_BASE_ADDR \ + (MVF_AIPS0_BASE_ADDR + 0x0007C000) +#define MVF_CAAM_SECMEM_END_ADDR \ + (MVF_AIPS0_BASE_ADDR + 0x0007FFFF) + #define L2_BASE_ADDR MVF_L2C_BASE_ADDR #define MVF_USBC0_CTRL_BASE_ADDR 0x40034800 @@ -563,15 +568,16 @@ #define MVF_INT_ESAI_BIFIFO 120 #define MVF_INT_SPDIF 121 #define MVF_INT_ASRC 122 -#define MVF_INT_CMU 123 +#define MVF_INT_CMU 123 #define MVF_INT_WKPU0 124 #define MVF_INT_WKPU1 125 -#define MVF_INT_CCM 126 +#define MVF_INT_CCM 126 -#define MVF_INT_SRC 128 -#define MVF_INT_PDB 129 -#define MVF_INT_EWM 130 +#define MVF_INT_SRC 128 +#define MVF_INT_PDB 129 +#define MVF_INT_EWM 130 #define MVF_INT_SNVS 132 +#define MVF_INT_SNVS_SEC 133 #define MVF_INT_CAAM 134 -- cgit v1.2.3 From 9d7ee1114441401aee095ca522d75ed530e2e894 Mon Sep 17 00:00:00 2001 From: Russell Robinson Jr Date: Tue, 27 Nov 2012 10:52:37 -0800 Subject: Initial phyCORE-Vybrid changes Signed-off-by: Russell Robinson Jr --- arch/arm/plat-mxc/include/mach/iomux-mvf.h | 56 +++++++++++++++++++---------- arch/arm/plat-mxc/include/mach/iomux-v3.h | 3 +- arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h | 2 +- 3 files changed, 41 insertions(+), 20 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h index b1bbb0955010..fbc0571f8b9f 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h @@ -47,7 +47,8 @@ typedef enum iomux_config { #define MVF600_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm) -#define MVF600_I2C_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH) +#define MVF600_I2C_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_ODE) #define MVF600_SAI_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_HYS | \ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) @@ -87,9 +88,9 @@ typedef enum iomux_config { IOMUX_PAD(0x0048, 0x0048, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) #define MVF600_PAD19_PTA29__SDHC1_DAT3 \ IOMUX_PAD(0x004C, 0x004C, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL) -/*set PTA7 as GPIO for sdhc card detecting*/ -#define MVF600_PAD134_PTA7__SDHC1_SW_CD \ - IOMUX_PAD(0x0218, 0x0218, 0, 0x0000, 0, \ +/*set PTD6 as GPIO for sdhc card detecting*/ +#define MVF600_PAD85_PTD6__SDHC1_SW_CD \ + IOMUX_PAD(0x0154, 0x0154, 0, 0x0000, 0, \ MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE) /*I2C0*/ @@ -99,6 +100,18 @@ typedef enum iomux_config { #define MVF600_PAD37_PTB15__I2C0_SDA \ IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, \ MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) +/*I2C2*/ +#define MVF600_PAD12_PTA22__I2C2_SCL \ + IOMUX_PAD(0x0030, 0x0030, 6, 0x034C, 0, \ + MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) +#define MVF600_PAD13_PTA23__I2C2_SDA \ + IOMUX_PAD(0x0034, 0x0034, 6, 0x0350, 0, \ + MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE) +/*CAN0*/ +#define MVF600_PAD36_PTB14__CAN0_RX \ + IOMUX_PAD(0x0090, 0x0090, 1, 0x0000, 0, 0) +#define MVF600_PAD37_PTB15__CAN0_TX \ + IOMUX_PAD(0x0094, 0x0094, 1, 0x0000, 0, 0) /*CAN1*/ #define MVF600_PAD38_PTB16__CAN1_RX \ @@ -183,12 +196,16 @@ typedef enum iomux_config { MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE) /*USB0/1 VBUS, using the GPIO*/ -#define MVF600_PAD85_PTD6__USB0_VBUS_EN \ - IOMUX_PAD(0x0154, 0x0154, 0, 0x0000, 0, \ - MVF600_GPIO_GENERAL_CTRL) -#define MVF600_PAD92_PTD13__USB1_VBUS_EN \ - IOMUX_PAD(0x0170, 0x0170, 0, 0x0000, 0, \ - MVF600_GPIO_GENERAL_CTRL) +#define MVF600_PAD134_PTA7__USB0_VBUS_EN \ + IOMUX_PAD(0x0218, 0x0218, 0, 0x0000, 0, \ + MVF600_GPIO_GENERAL_CTRL | PAD_CTL_OBE_ENABLE) +#define MVF600_PAD6_PTA16__USB0_VBUS_EN \ + IOMUX_PAD(0x0018, 0x0018, 0, 0x0000, 0, \ + MVF600_GPIO_GENERAL_CTRL | PAD_CTL_OBE_ENABLE) + +#define MVF600_PAD7_PTA17__USB_OC_N \ + IOMUX_PAD(0x001C, 0x001C, 2, 0x0000, 0, \ + PAD_CTL_DSE_20ohm | PAD_CTL_IBE_ENABLE) /*ESAI0(share with FEC1)*/ #define MVF600_PAD54_PTC9__ESAI_SCKT \ @@ -230,19 +247,22 @@ typedef enum iomux_config { #define MVF600_PAD11_PTA21_SAI2_RX_BCLK \ IOMUX_PAD(0x002C, 0x002C, 5, 0x0364, 0, \ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) -#define MVF600_PAD12_PTA22_SAI2_RX_DATA \ - IOMUX_PAD(0x0030, 0x0030, 5, 0x0368, 0, \ +#define MVF600_PAD23_PTB1_SAI2_RX_DATA \ + IOMUX_PAD(0x005C, 0x005C, 5, 0x0368, 1, \ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) -#define MVF600_PAD13_PTA23_SAI2_RX_SYNC \ - IOMUX_PAD(0x0034, 0x0034, 5, 0x036c, 0, \ +#define MVF600_PAD24_PTB2_SAI2_RX_SYNC \ + IOMUX_PAD(0x0060, 0x0060, 5, 0x036c, 1, \ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) #define MVF600_PAD40_PTB18_EXT_AUDIO_MCLK \ IOMUX_PAD(0x00A0, 0x00A0, 2, 0x02ec, 2, \ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) +#define MVF600_PAD33_PTB11__CKO2 \ + IOMUX_PAD(0x0084, 0x0084, 6, 0x24038, 0x040D, \ + MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE) /*DCU0*/ -#define MVF600_PAD30_PTB8_LCD_ENABLE \ - IOMUX_PAD(0x78, 0x78, 0, 0x0000, 0, MVF600_DCU_PAD_CTRL) +#define MVF600_PAD25_PTB3_LCD_ENABLE \ + IOMUX_PAD(0x64, 0x64, 0, 0x0000, 0, MVF600_DCU_PAD_CTRL) #define MVF600_PAD105_PTE0_DCU0_HSYNC \ IOMUX_PAD(0x01A4, 0x01A4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL) #define MVF600_PAD106_PTE1_DCU0_VSYNC \ @@ -335,8 +355,8 @@ typedef enum iomux_config { IOMUX_PAD(0x007C, 0x007C, 1, 0x0330, 0, MVF600_FTM1_CH_CTRL) /* Touch Screen */ -#define MVF600_PAD21_PTA31_TS_IRQ \ - IOMUX_PAD(0x0054, 0x0054, 0, 0x0000, 0, \ +#define MVF600_PAD32_PTB10_TS_IRQ \ + IOMUX_PAD(0x0080, 0x0080, 0, 0x0000, 0, \ MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE) /*QSPI*/ diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 78b8aa2503f5..97a8ca7c7f9a 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -116,7 +116,8 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_SRE_SLOW (0 << 0) #elif defined(CONFIG_ARCH_MVF) -#define PAD_CTL_SPEED_LOW (1 << 12) +/* FIXED: (1 << 12) is also MED (100 MHz according to TRM) */ +#define PAD_CTL_SPEED_LOW (0 << 12) #define PAD_CTL_SPEED_MED (2 << 12) #define PAD_CTL_SPEED_HIGH (3 << 12) diff --git a/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h b/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h index 9a5ba8e396a9..38fcdd4916bf 100644 --- a/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h +++ b/arch/arm/plat-mxc/include/mach/mvf-dcu-fb.h @@ -32,7 +32,7 @@ struct dfb_chroma_key { __u8 blue_min; }; -#define DCU_LCD_ENABLE_PIN 30 +#define DCU_LCD_ENABLE_PIN 25 #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key) #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8) -- cgit v1.2.3 From 139da31fb4b4d98f8fdb7f3a62662b73b9d8b705 Mon Sep 17 00:00:00 2001 From: Russell Robinson Jr Date: Mon, 17 Dec 2012 11:38:33 -0800 Subject: pcm052: enable EEPROM driver in config, fix TSC IRQs Signed-off-by: Russell Robinson Jr --- arch/arm/plat-mxc/include/mach/iomux-mvf.h | 4 ++-- arch/arm/plat-mxc/include/mach/irqs.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h index fbc0571f8b9f..a838e0bbead9 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h @@ -356,8 +356,8 @@ typedef enum iomux_config { /* Touch Screen */ #define MVF600_PAD32_PTB10_TS_IRQ \ - IOMUX_PAD(0x0080, 0x0080, 0, 0x0000, 0, \ - MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE) + IOMUX_PAD(0x0080, 0x0080, 0, 0x0000, 0, \ + PAD_CTL_SPEED_MED | PAD_CTL_IBE_ENABLE) /*QSPI*/ #define MVF600_PAD79_PTD0_QSPI0_A_SCK \ diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h index 9fce85784a32..4edd8d91c57d 100644 --- a/arch/arm/plat-mxc/include/mach/irqs.h +++ b/arch/arm/plat-mxc/include/mach/irqs.h @@ -74,7 +74,14 @@ #define MX5_IPU_IRQS 0 #endif +#ifdef CONFIG_MACH_PCM052 +#define STMPE_IRQ_BASE (MXC_IPU_IRQ_START) +#define STMPE_MAX_GPIOS 24 +#define STMPE_IRQ_END (STMPE_IRQ_BASE + STMPE_MAX_GPIOS) +#define NR_IRQS (STMPE_IRQ_END) +#else #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS + MX5_IPU_IRQS) +#endif extern int imx_irq_set_priority(unsigned char irq, unsigned char prio); -- cgit v1.2.3 From 960a5e572b76b51e1e6f184c2dae1394f0830bdc Mon Sep 17 00:00:00 2001 From: Russell Robinson Jr Date: Wed, 23 Jan 2013 10:37:10 -0800 Subject: pcm052: sdhc: fix drive strength and use only hardware pull-ups Signed-off-by: Russell Robinson Jr --- arch/arm/plat-mxc/include/mach/iomux-mvf.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h index a838e0bbead9..05932e3af1d2 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h @@ -40,9 +40,8 @@ typedef enum iomux_config { #define NON_MUX_I 0x3FF #define NON_PAD_I 0x7FF -#define MVF600_SDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ - PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) +#define MVF600_SDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) #define MVF600_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm) -- cgit v1.2.3 From 10d675e891b7969fe0658db17ad0ecc88fd6eda5 Mon Sep 17 00:00:00 2001 From: Russell Robinson Jr Date: Mon, 4 Feb 2013 14:12:45 -0800 Subject: pcm052: usb: fix VBUS enable mux settings and assert GPIO to enable VBUS Signed-off-by: Russell Robinson Jr --- arch/arm/plat-mxc/include/mach/iomux-mvf.h | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h index 05932e3af1d2..eb093e2c0f7f 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mvf.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h @@ -195,16 +195,19 @@ typedef enum iomux_config { MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE) /*USB0/1 VBUS, using the GPIO*/ -#define MVF600_PAD134_PTA7__USB0_VBUS_EN \ +#define MVF600_PAD134_PTA7__USB_VBUS_EN \ IOMUX_PAD(0x0218, 0x0218, 0, 0x0000, 0, \ - MVF600_GPIO_GENERAL_CTRL | PAD_CTL_OBE_ENABLE) + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_25ohm | \ + PAD_CTL_SPEED_LOW | PAD_CTL_OBE_ENABLE) #define MVF600_PAD6_PTA16__USB0_VBUS_EN \ IOMUX_PAD(0x0018, 0x0018, 0, 0x0000, 0, \ - MVF600_GPIO_GENERAL_CTRL | PAD_CTL_OBE_ENABLE) - + PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_25ohm | \ + PAD_CTL_SPEED_LOW | PAD_CTL_OBE_ENABLE) #define MVF600_PAD7_PTA17__USB_OC_N \ IOMUX_PAD(0x001C, 0x001C, 2, 0x0000, 0, \ - PAD_CTL_DSE_20ohm | PAD_CTL_IBE_ENABLE) + PAD_CTL_HYS | PAD_CTL_IBE_ENABLE) /*ESAI0(share with FEC1)*/ #define MVF600_PAD54_PTC9__ESAI_SCKT \ -- cgit v1.2.3 From fd5b59f7d6fc1736c2b00f306dcfeb574fea4512 Mon Sep 17 00:00:00 2001 From: Russell Robinson Jr Date: Mon, 11 Feb 2013 15:33:19 -0800 Subject: mvf: usb: create modular defines for ehci and some hardware address changes. ehci changes are currently only used with phyCORE-Vybrid (pcm052) Signed-off-by: Russell Robinson Jr --- arch/arm/plat-mxc/include/mach/arc_otg.h | 2 +- arch/arm/plat-mxc/include/mach/mvf.h | 19 ++++++++++++------- 2 files changed, 13 insertions(+), 8 deletions(-) (limited to 'arch/arm/plat-mxc/include') diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h index 51945e0fa957..af06f51759e5 100755 --- a/arch/arm/plat-mxc/include/mach/arc_otg.h +++ b/arch/arm/plat-mxc/include/mach/arc_otg.h @@ -31,7 +31,7 @@ extern void __iomem *imx_otg_base; #define USB_OTGREGS_BASE MVF_IO_ADDRESS(0x40034000) #define USB_OTG2REGS_BASE MVF_IO_ADDRESS(0x400B4000) -#define USB_H1REGS_BASE MVF_IO_ADDRESS(0x400B4000) +#define USB_H1REGS_BASE MVF_IO_ADDRESS(0x40034000) /* dummy h2regs for MVF */ #define USB_H2REGS_BASE MVF_IO_ADDRESS(0x400B4000) #define USBC0_OTHERREGS_BASE MVF_IO_ADDRESS(0x40034800) diff --git a/arch/arm/plat-mxc/include/mach/mvf.h b/arch/arm/plat-mxc/include/mach/mvf.h index 838eef400e95..4a47636fa741 100644 --- a/arch/arm/plat-mxc/include/mach/mvf.h +++ b/arch/arm/plat-mxc/include/mach/mvf.h @@ -183,14 +183,14 @@ #define L2_BASE_ADDR MVF_L2C_BASE_ADDR -#define MVF_USBC0_CTRL_BASE_ADDR 0x40034800 -#define MVF_USBC1_CTRL_BASE_ADDR 0x400B4800 -#define MVF_USBC0_PHY_BASE_ADDR 0x40034818 -#define MVF_USBC1_PHY_BASE_ADDR 0x400B4818 +#define MVF_USBC0_CTRL_BASE_ADDR 0x40035800 +#define MVF_USBC1_CTRL_BASE_ADDR 0x400B5800 +#define MVF_USBC0_PHY_BASE_ADDR 0x40035818 +#define MVF_USBC1_PHY_BASE_ADDR 0x400B5818 #define MVF_USBC0_BASE_ADDR 0x40034000 #define MVF_USBC1_BASE_ADDR 0x400B4000 #define MVF_USBPHY0_BASE_ADDR 0x40050800 -#define MVF_USBPHY1_BASE_ADDR 0x40050B00 +#define MVF_USBPHY1_BASE_ADDR 0x40050C00 #define MVF_MSCM_INT_ROUTER_BASE (MVF_MSCM_BASE_ADDR + 0x800) @@ -553,8 +553,13 @@ #define MVF_INT_I2C1 104 #define MVF_INT_I2C2 105 #define MVF_INT_I2C3 106 -#define MVF_INT_USBOTG0 107 -#define MVF_INT_USB2 108 + +#ifdef CONFIG_MACH_PCM052 +#define MVF_INT_USB0 107 +#define MVF_INT_USB1 108 +#else +#endif + #define MVF_INT_ENET_MAC0 110 #define MVF_INT_ENET_MAC1 111 #define MVF_INT_1588_TIMER0 112 -- cgit v1.2.3