From 68437fa5d8cf810c58643b364f906cb7ae29561f Mon Sep 17 00:00:00 2001 From: Scott Williams Date: Wed, 3 Aug 2011 17:33:37 -0700 Subject: ARM: tegra: power: Add SMP coherency exit macro Define the SMP coherency exit code as a macro to allow it to be inlined in assembly code that needs to control its register usage. Change-Id: If5bd01241a92eb471cf59b4fc8445934fd4932b1 Signed-off-by: Scott Williams Rebase-Id: R921ed4d46431115d164f73bacac16a68a9d32b0a --- arch/arm/mach-tegra/sleep.S | 12 +----------- arch/arm/mach-tegra/sleep.h | 20 +++++++++++++++++++- 2 files changed, 20 insertions(+), 12 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 36dff782f3fa..9b436c9512a2 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -47,7 +47,6 @@ #define CLK_RESET_CCLK_DIVIDER 0x24 #define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT) -#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT) #define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) /* @@ -139,16 +138,7 @@ ENDPROC(tegra_cpu_wfi) * corrupts r4-r5 */ ENTRY(tegra_cpu_exit_coherency) - mrc p15, 0, r4, c1, c0, 1 @ ACTLR - bic r4, r4, #(1<<6) @ exit coherency: clear ACTLR.SMP - mcr p15, 0, r4, c1, c0, 1 @ ACTLR - isb - cpu_id r4 - mov r4, r4, lsl #2 - mov r5, #0xf - mov r5, r5, lsl r4 - mov32 r4, TEGRA_ARM_PERIF_VIRT + 0xC - str r5, [r4] @ invalidate SCU tags for CPU + exit_smp r4, r5 mov pc, lr ENDPROC(tegra_cpu_exit_coherency) diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index a6f6b1740009..02ab870edbbe 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -74,8 +74,26 @@ #endif #define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) +#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT) + +#ifdef __ASSEMBLY__ + +/* Macro to exit SMP coherency. */ +.macro exit_smp, tmp1, tmp2 + mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR + bic \tmp1, \tmp1, #(1<<6) @ clear ACTLR.SMP + mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR + isb + cpu_id \tmp1 + mov \tmp1, \tmp1, lsl #2 + mov \tmp2, #0xf + mov \tmp2, \tmp2, lsl \tmp1 + mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC + str \tmp2, [\tmp1] @ invalidate SCU tags for CPU + dsb +.endm -#ifndef __ASSEMBLY__ +#else #define FLOW_CTRL_HALT_CPU(cpu) (IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + \ ((cpu) ? (FLOW_CTRL_HALT_CPU1_EVENTS + 8 * ((cpu) - 1)) : \ -- cgit v1.2.3