From 96173a6c4ebca4c146bb87026cce78bbe392cb61 Mon Sep 17 00:00:00 2001 From: Thomas Bogendoerfer Date: Thu, 17 Apr 2008 22:07:42 +0200 Subject: [MIPS] IP27: misc fixes - fix PCI interrupt assignment by emulating ioc3 interrupt pin register - use pci_probe_only mode - select correct page size in bridge - remove no longer needed ioc3_sio_init() code [Ralf: Fix for 64kB or larger pagesizes] Signed-off-by: Thomas Bogendoerfer Signed-off-by: Ralf Baechle --- arch/mips/pci/ops-bridge.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'arch/mips/pci/ops-bridge.c') diff --git a/arch/mips/pci/ops-bridge.c b/arch/mips/pci/ops-bridge.c index 1fa09929cd7a..b46b3e211775 100644 --- a/arch/mips/pci/ops-bridge.c +++ b/arch/mips/pci/ops-bridge.c @@ -13,6 +13,22 @@ #include #include +/* + * Most of the IOC3 PCI config register aren't present + * we emulate what is needed for a normal PCI enumeration + */ +static u32 emulate_ioc3_cfg(int where, int size) +{ + if (size == 1 && where == 0x3d) + return 0x01; + else if (size == 2 && where == 0x3c) + return 0x0100; + else if (size == 4 && where == 0x3c) + return 0x00000100; + + return 0; +} + /* * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is * not really documented, so right now I can't write code which uses it. @@ -64,7 +80,7 @@ oh_my_gawd: * generic PCI code a chance to look at the wrong register. */ if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { - *value = 0; + *value = emulate_ioc3_cfg(where, size); return PCIBIOS_SUCCESSFUL; } @@ -127,7 +143,7 @@ oh_my_gawd: * generic PCI code a chance to look at the wrong register. */ if ((where >= 0x14 && where < 0x40) || (where >= 0x48)) { - *value = 0; + *value = emulate_ioc3_cfg(where, size); return PCIBIOS_SUCCESSFUL; } -- cgit v1.2.3