From 08139881d07bec1f0e419c0e49f10b84250ebc21 Mon Sep 17 00:00:00 2001 From: Joseph Lo Date: Thu, 29 Mar 2012 14:46:33 +0800 Subject: ARM: tegra: cpu: enable VDD_CPU rail before LP to G transition When doing LP to G transition, it had a power up latency on VDD_CPU rail. To reduce the latency, CPU_LP can trun on the VDD_CPU rail before the LP to G transition. Bug 930985 Change-Id: I087e185ea5aa90f309b8cafba9bc4bb7d3fc950c Signed-off-by: Joseph Lo Reviewed-on: http://git-master/r/93141 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Antti Miettinen Tested-by: Antti Miettinen GVS: Gerrit_Virtual_Submit Reviewed-by: Juha Tukkinen --- arch/arm/mach-tegra/pm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 054eb3aea358..7a08bc1aef24 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -140,6 +140,11 @@ struct suspend_context tegra_sctx; #define PMC_CPUPWROFF_TIMER 0xcc #define PMC_COREPWROFF_TIMER PMC_WAKE_DELAY +#define PMC_PWRGATE_TOGGLE 0x30 +#define PWRGATE_TOGGLE_START (1 << 8) +#define UN_PWRGATE_CPU \ + (PWRGATE_TOGGLE_START | TEGRA_CPU_POWERGATE_ID(TEGRA_POWERGATE_CPU)) + #ifdef CONFIG_TEGRA_CLUSTER_CONTROL #define PMC_SCRATCH4_WAKE_CLUSTER_MASK (1<<31) #endif @@ -597,6 +602,16 @@ unsigned int tegra_idle_lp2_last(unsigned int sleep_time, unsigned int flags) trace_cpu_cluster(POWER_CPU_CLUSTER_START); set_power_timers(pdata->cpu_timer, 0, clk_get_rate_all_locked(tegra_pclk)); + if (flags & TEGRA_POWER_CLUSTER_G) { + /* + * To reduce the vdd_cpu up latency when LP->G + * transition. Before the transition, enable + * the vdd_cpu rail. + */ + if (is_lp_cluster()) + writel(UN_PWRGATE_CPU, + pmc + PMC_PWRGATE_TOGGLE); + } tegra_cluster_switch_prolog(flags); } else { set_power_timers(pdata->cpu_timer, pdata->cpu_off_timer, -- cgit v1.2.3