From ca0eb6c1daef8dc485870596fb6c21354fcbe1e8 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Wed, 11 Apr 2012 11:20:20 -0700 Subject: ARM: errata: 716044: an uncacheable load multiple can cause a deadlock. Under some rare circumstances, an uncacheable load multiple instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause a processor deadlock. Change-Id: Ibd79aa8182dce37d0be9892f2310735e1123618a Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/95914 Reviewed-by: Varun Colbert Tested-by: Varun Colbert --- arch/arm/Kconfig | 8 ++++++++ arch/arm/mm/proc-v7.S | 6 ++++++ 2 files changed, 14 insertions(+) (limited to 'arch') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3c3b868948aa..fcbd87b17507 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1155,6 +1155,14 @@ config ARM_ERRATA_460075 ACTLR register. Note that setting specific bits in the ACTLR register may not be available in non-secure mode. +config ARM_ERRATA_716044 + bool "ARM errata: an uncacheable load multiple instruction can cause a deadlock" + depends on CPU_V7 + help + Under some rare circumstances, an uncacheable load multiple + instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause + a processor deadlock. + config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" depends on CPU_V7 && SMP diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 38c78253f769..a502958a71f8 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -551,6 +551,12 @@ __v7_setup: mrcge p15, 0, r10, c15, c0, 0 @ read power control register orrge r10, r10, #1 @ enable dynamic clock gating mcrge p15, 0, r10, c15, c0, 0 @ write power control register +#ifdef CONFIG_ARM_ERRATA_716044 + cmp r6, #0x12 @ present in r1p0 - r1p2 + mrcle p15, 0, r10, c1, c0, 0 + orrle r10, r10, #(1 << 14) @ set SCTLR.RR + mcrle p15, 0, r10, c1, c0, 0 +#endif #ifdef CONFIG_ARM_ERRATA_720791 teq r5, #0x00100000 @ only present in r1p* mrceq p15, 0, r10, c15, c0, 2 @ read "chicken power ctrl" reg -- cgit v1.2.3