From e892c1daa8da1c1c342759ef18add40397136003 Mon Sep 17 00:00:00 2001 From: Mohit Kataria Date: Mon, 9 Apr 2012 11:49:27 +0530 Subject: Arm: Tegra: Nor: use timing1 proper value timing1_read was initialized with timing0 from nor platform data changed the same to use timing1 from platform data instead of timing0 Bug 934187 Change-Id: I04c41323de25fb2bb53dac91301cee9c0820707a Signed-off-by: Mohit Kataria Reviewed-on: http://git-master/r/95293 Reviewed-on: http://git-master/r/100904 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amlan Kundu Reviewed-by: Varun Wadekar --- drivers/mtd/maps/tegra_nor.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/mtd') diff --git a/drivers/mtd/maps/tegra_nor.c b/drivers/mtd/maps/tegra_nor.c index b455fd5e1c00..cc80a0bb3e86 100644 --- a/drivers/mtd/maps/tegra_nor.c +++ b/drivers/mtd/maps/tegra_nor.c @@ -279,7 +279,7 @@ static int tegra_snor_controller_init(struct tegra_nor_info *info) info->timing0_default = chip_parm->timing_default.timing0; info->timing0_read = chip_parm->timing_read.timing0; info->timing1_default = chip_parm->timing_default.timing1; - info->timing1_read = chip_parm->timing_read.timing0; + info->timing1_read = chip_parm->timing_read.timing1; snor_tegra_writel(info, info->timing1_default, TEGRA_SNOR_TIMING1_REG); snor_tegra_writel(info, info->timing0_default, TEGRA_SNOR_TIMING0_REG); -- cgit v1.2.3