From 04875177dbe034055f23960981ecf6fb8ea1d638 Mon Sep 17 00:00:00 2001 From: Sinan Kaya Date: Mon, 22 Jan 2018 15:12:01 -0500 Subject: PCI/ASPM: Don't warn if already in common clock mode Previously we emitted a warning if we tried to configure common clock mode the link was already configured to common clock mode by the UEFI BIOS. Bail out silently in that case instead of emitting the warning: pci 0004:00:00.0: ASPM: Could not configure common clock Signed-off-by: Sinan Kaya [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas --- drivers/pci/pcie/aspm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/pci/pcie/aspm.c') diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 8633fc4e1c11..95a2f222b64e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -228,6 +228,24 @@ static void pcie_aspm_configure_common_clock(struct pcie_link_state *link) if (!(reg16 & PCI_EXP_LNKSTA_SLC)) same_clock = 0; + /* Port might be already in common clock mode */ + pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16); + if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) { + bool consistent = true; + + list_for_each_entry(child, &linkbus->devices, bus_list) { + pcie_capability_read_word(child, PCI_EXP_LNKCTL, + ®16); + if (!(reg16 & PCI_EXP_LNKCTL_CCC)) { + consistent = false; + break; + } + } + if (consistent) + return; + pci_warn(parent, "ASPM: current common clock configuration is broken, reconfiguring\n"); + } + /* Configure downstream component, all functions */ list_for_each_entry(child, &linkbus->devices, bus_list) { pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16); -- cgit v1.2.3