From 486f0b8253a8f58fd77f624a162785f20f9a70c5 Mon Sep 17 00:00:00 2001 From: David Schalig Date: Thu, 10 Mar 2011 21:49:33 +0900 Subject: [TPS658x RTC] Correct reg RTC_CTRL usage Correct PRE_BYPASS (clock scaler 32kHz/1kHz select) bitfield. Add platform data to tune RTC XTAL capacitance in board file. Bug 798832, Tested on Ventana/wake via Alarm Clock Original-Change-Id: I82d67610a815866707fc1db934d7d4d7cf93d883 Reviewed-on: http://git-master/r/22402 Reviewed-by: Varun Colbert Tested-by: Varun Colbert Reviewed-by: David Schalig Reviewed-by: Jonathan Mayo Rebase-Id: Rf54ae72ccdf2538dcaed60590aa98780a365628b --- drivers/rtc/rtc-tps6586x.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) (limited to 'drivers/rtc/rtc-tps6586x.c') diff --git a/drivers/rtc/rtc-tps6586x.c b/drivers/rtc/rtc-tps6586x.c index d5280d050d4b..3f6e2a9a3d84 100644 --- a/drivers/rtc/rtc-tps6586x.c +++ b/drivers/rtc/rtc-tps6586x.c @@ -30,8 +30,13 @@ #include #define RTC_CTRL 0xc0 +#define POR_RESET_N BIT(7) +#define OSC_SRC_SEL BIT(6) #define RTC_ENABLE BIT(5) /* enables alarm */ -#define RTC_HIRES BIT(4) /* 1Khz or 32Khz updates */ +#define RTC_BUF_ENABLE BIT(4) /* 32 KHz buffer enable */ +#define PRE_BYPASS BIT(3) /* 0=1KHz or 1=32KHz updates */ +#define CL_SEL_MASK (BIT(2)|BIT(1)) +#define CL_SEL_POS 1 #define RTC_ALARM1_HI 0xc1 #define RTC_COUNT4 0xc6 @@ -284,9 +289,10 @@ static int __devinit tps6586x_rtc_probe(struct platform_device *pdev) goto fail; } - /* disable high-res mode, enable tick counting */ + /* 1 kHz tick mode, enable tick counting */ err = tps6586x_update(tps_dev, RTC_CTRL, - (RTC_ENABLE | RTC_HIRES), RTC_ENABLE); + RTC_ENABLE | ((pdata->cl_sel<dev, "unable to start counter\n"); goto fail; -- cgit v1.2.3