From b901b56e0c0573ce30393836e4078ca78beffca0 Mon Sep 17 00:00:00 2001 From: Kevin Huang Date: Wed, 6 Jun 2012 10:48:18 -0700 Subject: video: tegra: dc: Clock-gate display modules dynamically. Bug 936337 Bug 899053 Change-Id: I2b3d8cfc8a00881338c1e17d03f2844d15ba7d3e Signed-off-by: Kevin Huang Reviewed-on: http://git-master/r/106313 Reviewed-by: Simone Willett Tested-by: Simone Willett --- drivers/video/tegra/dc/dc_priv.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/video/tegra/dc/dc_priv.h') diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h index 4f53f60f2599..06f2a6061bf6 100644 --- a/drivers/video/tegra/dc/dc_priv.h +++ b/drivers/video/tegra/dc/dc_priv.h @@ -32,6 +32,7 @@ #include "../host/host1x/host1x_syncpt.h" #include +#include #define WIN_IS_TILED(win) ((win)->flags & TEGRA_WIN_FLAG_TILED) #define WIN_IS_ENABLED(win) ((win)->flags & TEGRA_WIN_FLAG_ENABLED) @@ -164,6 +165,9 @@ static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, unsigned long ret; BUG_ON(!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)); + if (!tegra_is_clk_enabled(dc->clk)) + WARN(1, "DC is clock-gated.\n"); + ret = readl(dc->base + reg * 4); trace_printk("readl %p=%#08lx\n", dc->base + reg * 4, ret); return ret; @@ -173,6 +177,9 @@ static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long val, unsigned long reg) { BUG_ON(!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)); + if (!tegra_is_clk_enabled(dc->clk)) + WARN(1, "DC is clock-gated.\n"); + trace_printk("writel %p=%#08lx\n", dc->base + reg * 4, val); writel(val, dc->base + reg * 4); } -- cgit v1.2.3