From f56b81ec82be9c22f66eaf853720f8759a8cd57f Mon Sep 17 00:00:00 2001 From: Xin Xie Date: Thu, 7 Jul 2011 14:05:04 -0700 Subject: video: tegra: dc: fix tiled memory efficiency Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3. This patch adds one memory controller API to retrive tiled memory efficiency. BUG 847731 Original-Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1 Reviewed-on: http://git-master/r/40074 Reviewed-by: Varun Colbert Tested-by: Varun Colbert Rebase-Id: R5675398d3066d01d3d46f26267eddbba1accc815 --- drivers/video/tegra/dc/dc_priv.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'drivers/video/tegra/dc/dc_priv.h') diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h index 9868cb850dba..c353680ffc96 100644 --- a/drivers/video/tegra/dc/dc_priv.h +++ b/drivers/video/tegra/dc/dc_priv.h @@ -40,18 +40,6 @@ #define EMC_BW_TO_FREQ(bw) (DDR_BW_TO_FREQ(bw) * 2) #endif -/* - * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is - * discarded in tiling mode. - */ -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) -#define TILED_WINDOWS_BW_MULTIPLIER 1 -#elif defined(CONFIG_ARCH_TEGRA_3x_SOC) -#define TILED_WINDOWS_BW_MULTIPLIER 2 -#else -#warning "need to revisit memory tiling effects on DC" -#endif - struct tegra_dc; struct tegra_dc_blend { -- cgit v1.2.3