From 409dce46df80f7ace06187c5879e15aa99494a9a Mon Sep 17 00:00:00 2001 From: Roger Hsieh Date: Tue, 3 Jul 2012 15:13:31 +0800 Subject: tegra: dc: Make data output along with pixel clock. After making pclk output ahead of LVDS_SHDN# , data output is later than panel ready then caused partial black screen. Force triggered data output to get it fixed. Bug 972377 Bug 976081 Bug 1001434 Change-Id: Icd455d7439f622e46295158a5435286c521526aa Signed-off-by: Roger Hsieh Reviewed-on: http://git-master/r/113164 Reviewed-by: Rohan Somvanshi Tested-by: Rohan Somvanshi --- drivers/video/tegra/dc/dc.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers/video') diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c index 77cd19e6f870..1f7e2ce67682 100644 --- a/drivers/video/tegra/dc/dc.c +++ b/drivers/video/tegra/dc/dc.c @@ -1286,15 +1286,19 @@ static bool _tegra_dc_controller_enable(struct tegra_dc *dc) if (dc->out_ops && dc->out_ops->enable) dc->out_ops->enable(dc); - if (dc->out->postpoweron) - dc->out->postpoweron(); - /* force a full blending update */ dc->blend.z[0] = -1; tegra_dc_ext_enable(dc->ext); trace_printk("%s:enable\n", dc->ndev->name); + + tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + + if (dc->out->postpoweron) + dc->out->postpoweron(); + return true; } -- cgit v1.2.3