From e31b6c721e35a75e34818338f9d581159315ecec Mon Sep 17 00:00:00 2001 From: Nikesh Oswal Date: Tue, 6 Mar 2012 16:04:24 +0530 Subject: asoc: ap20: change i2s bitclk for dsp mode i2s bitclk for dsp mode was kept 4 times the minimum requirement for bcm4330 bt chip on whistler we require only 2 times the minimum requirement because modem is also configured similarly and for bt call both the bit clocks should match Change-Id: I6a84b22c9fbd66b4e60832933b508fe8cf21f387 Reviewed-on: http://git-master/r/88013 Tested-by: Nikesh Oswal Reviewed-by: Scott Peterson --- sound/soc/tegra/tegra20_i2s.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'sound') diff --git a/sound/soc/tegra/tegra20_i2s.c b/sound/soc/tegra/tegra20_i2s.c index 9ebe36795b07..e6de1c07a399 100644 --- a/sound/soc/tegra/tegra20_i2s.c +++ b/sound/soc/tegra/tegra20_i2s.c @@ -27,7 +27,7 @@ * 02110-1301 USA * */ - +#include #include #include #include @@ -222,7 +222,7 @@ static int tegra20_i2s_hw_params(struct snd_pcm_substream *substream, i2sclock = srate * params_channels(params) * sample_size * 2; /* Additional "* 2" is needed for DSP mode */ - if (i2s->reg_ctrl & TEGRA20_I2S_CTRL_BIT_FORMAT_DSP) + if (i2s->reg_ctrl & TEGRA20_I2S_CTRL_BIT_FORMAT_DSP && !machine_is_whistler()) i2sclock *= 2; ret = clk_set_rate(i2s->clk_i2s, i2sclock); -- cgit v1.2.3