/*
 * Copyright 2015-2016 Freescale Semiconductor, Inc.
 * Copyright 2016 Toradex AG
 * Copyright 2017-2018 NXP
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "imx7s.dtsi"
#include <dt-bindings/reset/imx7-reset.h>

/ {
	cpus {
		cpu0: cpu@0 {
			operating-points = <
				/* KHz	uV */
				1200000	1225000
				996000	1075000
				792000	975000
			>;
			clock-frequency = <996000000>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
			clock-frequency = <996000000>;
		};
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x14000000>;
			linux,cma-default;
		};
	};

	soc {
		etm@3007d000 {
			compatible = "arm,coresight-etm3x", "arm,primecell";
			reg = <0x3007d000 0x1000>;

			/*
			 * System will hang if added nosmp in kernel command line
			 * without arm,primecell-periphid because amba bus try to
			 * read id and core1 power off at this time.
			 */
			arm,primecell-periphid = <0xbb956>;
			cpu = <&cpu1>;
			clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
			clock-names = "apb_pclk";

			port {
				etm1_out_port: endpoint {
					remote-endpoint = <&ca_funnel_in_port1>;
				};
			};
		};

		busfreq {
			compatible = "fsl,imx_busfreq";
			fsl,max_ddr_freq = <533000000>;
			clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>,
				<&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>,
				<&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>,
				<&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>,
				<&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>,
				<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>;
			clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel",
					"pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi";
			interrupts = <0 112 0x04>, <0 113 0x04>;
			interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
		};

		caam_sm: caam-sm@00100000 {
			 compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
			 reg = <0x00100000 0x8000>;
		};

		irq_sec_vio: caam_secvio {
			compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			jtag-tamper = "disabled";
			watchdog-tamper = "enabled";
			internal-boot-tamper = "enabled";
			external-pin-tamper = "disabled";
		};

		pmu {
			compatible = "arm,cortex-a7-pmu";
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ocrams_ddr: sram@00900000 {
			compatible = "fsl,ddr-lpm-sram";
			reg = <0x00900000 0x1000>;
			clocks = <&clks IMX7D_OCRAM_CLK>;
		};

		ocram: sram@901000 {
			compatible = "mmio-sram";
			reg = <0x00901000 0x1f000>;
			clocks = <&clks IMX7D_OCRAM_CLK>;
		};

		ocrams: sram@00180000 {
			compatible = "fsl,lpm-sram";
			reg = <0x00180000 0x8000>;
			clocks = <&clks IMX7D_OCRAM_S_CLK>;
			status = "disabled";
		};

		ocrams_mf: sram-mf@00900000 {
			compatible = "fsl,mega-fast-sram";
			reg = <0x00900000 0x20000>;
			clocks = <&clks IMX7D_OCRAM_CLK>;
		};

		ocram_optee {
			compatible = "fsl,optee-lpm-sram";
			reg = <0x00180000 0x8000>;
			overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
					<&ocram 0x00905000 0x1b000>,
					<&ocrams 0x00900000 0x4000>;
			overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
		};
	};
};

&aips1 {
	kpp: kpp@30320000 {
		compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
		reg = <0x30320000 0x10000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_CLK_DUMMY>;
		status = "disabled";
	};

	mqs: mqs {
		compatible = "fsl,imx6sx-mqs";
		gpr = <&gpr>;
		status = "disabled";
	};

	ocotp: ocotp-ctrl@30350000 {
		compatible = "fsl,imx7d-ocotp", "syscon";
		reg = <0x30350000 0x10000>;
		clocks = <&clks IMX7D_OCOTP_CLK>;
		status = "okay";
	};

	tempmon: tempmon {
		compatible = "fsl,imx7d-tempmon";
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		fsl,tempmon =<&anatop>;
		fsl,tempmon-data = <&ocotp>;
		clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
	};

	caam_snvs: caam-snvs@30370000 {
		compatible = "fsl,imx6q-caam-snvs";
		reg = <0x30370000 0x10000>;
	};
	iomuxc_lpsr_gpr: lpsr-gpr@30270000 {
		compatible = "fsl,imx7d-lpsr-gpr";
		reg = <0x30270000 0x10000>;
	};
};

&aips2 {
	flextimer1: flextimer@30640000 {
		compatible = "fsl,imx7d-flextimer";
		reg = <0x30640000 0x10000>;
		interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	flextimer2: flextimer@30650000 {
		compatible = "fsl,imx7d-flextimer";
		reg = <0x30650000 0x10000>;
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	system_counter_rd: system-counter-rd@306a0000 {
		compatible = "fsl,imx7d-system-counter-rd";
		reg = <0x306a0000 0x10000>;
		status = "disabled";
	};

	system_counter_cmp: system-counter-cmp@306b0000 {
		compatible = "fsl,imx7d-system-counter-cmp";
		reg = <0x306b0000 0x10000>;
		status = "disabled";
	};

	system_counter_ctrl: system-counter-ctrl@306c0000 {
		compatible = "fsl,imx7d-system-counter-ctrl";
		reg = <0x306c0000 0x10000>;
		interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	epdc: epdc@306f0000 {
		compatible = "fsl,imx7d-epdc";
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x306f0000 0x10000>;
		clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>;
		clock-names = "epdc_axi", "epdc_pix";
		epdc-ram = <&gpr 0x4 30>;
		qos = <&qosc>;
		status = "disabled";
	};

	epxp: epxp@30700000 {
		compatible = "fsl,imx7d-pxp-dma";
		interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x30700000 0x10000>;
		clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
		clock-names = "pxp_ipg", "pxp_axi";
		status = "disabled";
	};

	csi1: csi@30710000 {
		compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
		reg = <0x30710000 0x10000>;
		interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_CLK_DUMMY>,
			<&clks IMX7D_CSI_MCLK_ROOT_CLK>,
			<&clks IMX7D_CLK_DUMMY>;
		clock-names = "disp-axi", "csi_mclk", "disp_dcic";
		status = "disabled";
	};

	mipi_csi: mipi-csi@30750000 {
		compatible = "fsl,imx7d-mipi-csi";
		reg = <0x30750000 0x10000>;
		interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
				<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
		clock-names = "mipi_clk", "phy_clk";
		mipi-phy-supply = <&reg_1p0d>;
		csis-phy-reset = <&src 0x28 2>;
		bus-width = <4>;
		status = "disabled";
	};

	mipi_dsi: mipi-dsi@30760000 {
		compatible = "fsl,imx7d-mipi-dsi";
		reg = <0x30760000 0x10000>;
		interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
			<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
		clock-names = "mipi_cfg_clk", "mipi_pllref_clk";
		mipi-phy-supply = <&reg_1p0d>;
		status = "disabled";
	};

	ddrc: ddrc@307a0000 {
		compatible = "fsl,imx7-ddrc";
		reg = <0x307a0000 0x10000>;
	};

	qosc: qosc@307f0000 {
		compatible = "fsl,imx7d-qosc", "syscon";
		reg = <0x307f0000 0x4000>;
	};
};

&aips3 {
	usbotg2: usb@30b20000 {
		compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
		reg = <0x30b20000 0x200>;
		interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_USB_CTRL_CLK>;
		fsl,usbphy = <&usbphynop2>;
		fsl,usbmisc = <&usbmisc2 0>;
		phy-clkgate-delay-us = <400>;
		ahb-burst-config = <0x0>;
		tx-burst-size-dword = <0x10>;
		rx-burst-size-dword = <0x10>;
		status = "disabled";
	};

	usbmisc2: usbmisc@30b20200 {
		#index-cells = <1>;
		compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
		reg = <0x30b20200 0x200>;
	};

	usbphynop2: usbphynop2 {
		compatible = "usb-nop-xceiv";
		clocks = <&clks IMX7D_USB_PHY2_CLK>;
		clock-names = "main_clk";
	};

	fec2: ethernet@30bf0000 {
		compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
		reg = <0x30bf0000 0x10000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
			<&clks IMX7D_ENET_AXI_ROOT_CLK>,
			<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
			<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
			<&clks IMX7D_ENET_PHY_REF_ROOT_DIV>;
		clock-names = "ipg", "ahb", "ptp",
			"enet_clk_ref", "enet_out";
		fsl,num-tx-queues=<3>;
		fsl,num-rx-queues=<3>;
		status = "disabled";
	};

	pcie: pcie@0x33800000 {
		compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
		reg = <0x33800000 0x4000>,
		      <0x306d0000 0x10000>,
		      <0x4ff00000 0x80000>;
		reg-names = "dbi", "phy", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x81000000 0 0          0x4ff80000 0 0x00010000   /* downstream I/O */
			  0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
		num-lanes = <1>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
		interrupt-names = "msi";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0x7>;
		/*
		 * Reference manual lists pci irqs incorrectly
		 * Real hardware ordering is same as imx6: D+MSI, C, B, A
		 */
		interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				<0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
			 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
			 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
		clock-names = "pcie", "pcie_bus", "pcie_phy";
		assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
				  <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
		assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
					 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;

		fsl,max-link-speed = <2>;
		power-domains = <&pgc_pcie_phy>;
		resets = <&src IMX7_RESET_PCIEPHY>,
			 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
		reset-names = "pciephy", "apps";
		status = "disabled";
	};

	crypto: caam@30900000 {
		compatible = "fsl,imx7d-caam", "fsl,sec-v4.0";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x30900000 0x40000>;
		ranges = <0 0x30900000 0x40000>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_CAAM_CLK>,
			<&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
		clock-names = "ipg", "aclk";

		sec_ctrl: ctrl@0 {
			/* CAAM Page 0 only accessible */
			/*	by secure world */
			compatible = "fsl,sec-v4.0-ctrl";
			reg = <0x30900000 0x1000>;
			secure-status = "okay";
			status = "disabled";
		};

		sec_jr0: jr0@1000 {
			 compatible = "fsl,sec-v4.0-job-ring";
			 reg = <0x1000 0x1000>;
			 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		};

		sec_jr1: jr1@2000 {
			 compatible = "fsl,sec-v4.0-job-ring";
			 reg = <0x2000 0x1000>;
			 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		};

		sec_jr2: jr2@3000 {
			 compatible = "fsl,sec-v4.0-job-ring";
			 reg = <0x3000 0x1000>;
			 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

	mu: mu@30aa0000 {
		compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu";
		reg = <0x30aa0000 0x10000>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_MU_ROOT_CLK>;
		clock-names = "mu";
		status = "okay";
	};

	rpmsg: rpmsg{
		compatible = "fsl,imx7d-rpmsg";
		status = "disabled";
	};

	sema4: sema4@30ac0000 {
		compatible = "fsl,imx7d-sema4";
		reg = <0x30ac0000 0x10000>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>;
		clock-names = "sema4";
		status = "okay";
	};

	sim1: sim@30b90000 {
		compatible = "fsl,imx7d-sim";
		reg = <0x30b90000 0x10000>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_SIM1_ROOT_CLK>;
		clock-names = "sim";
		status = "disabled";
	};

	sim2: sim@30ba0000 {
		compatible = "fsl,imx7d-sim";
		reg = <0x30ba0000 0x10000>;
		interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	qspi1: qspi@30bb0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "fsl,imx7d-qspi";
		reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>;
		reg-names = "QuadSPI", "QuadSPI-memory";
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_QSPI_ROOT_CLK>,
			<&clks IMX7D_QSPI_ROOT_CLK>;
		clock-names = "qspi_en", "qspi";
		status = "disabled";
	};

	weim: weim@30bc0000 {
		compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim";
		reg = <0x30bc0000 0x10000>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clks IMX7D_EIM_ROOT_CLK>;
		status = "disabled";
	};

};

&usbphynop3 {
	vcc-supply = <&reg_1p2>;
};

&ca_funnel_ports {
	port@1 {
		reg = <1>;
		ca_funnel_in_port1: endpoint {
			slave-mode;
			remote-endpoint = <&etm1_out_port>;
		};
	};
};