/* * Copyright 2015-2016 Freescale Semiconductor, Inc. * Copyright 2016 Toradex AG * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include "imx7s.dtsi" / { cpus { cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; }; }; etm@1,3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; arm,primecell-periphid = <0xbb956>; cpu = <&cpu1>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; port { etm1_out_port: endpoint { remote-endpoint = <&ca_funnel_in_port1>; }; }; }; }; &aips3 { usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b20000 0x200>; interrupts = ; clocks = <&clks IMX7D_USB_CTRL_CLK>; fsl,usbphy = <&usbphy_nop2>; fsl,usbmisc = <&usbmisc2 0>; phy-clkgate-delay-us = <400>; status = "disabled"; }; usbmisc2: usbmisc@30b20200 { #index-cells = <1>; compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x30b20200 0x200>; }; usbphy_nop2: usbphy_nop2 { compatible = "usb-nop-xceiv"; clocks = <&clks IMX7D_USB_PHY2_CLK>; clock-names = "main_clk"; }; fec2: ethernet@30bf0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30bf0000 0x10000>; interrupts = , , ; clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; stop-mode = <&gpr 0x10 4>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; fsl,wakeup_irq = <2>; status = "disabled"; }; }; &funnel_ports { port@1 { reg = <1>; ca_funnel_in_port1: endpoint { slave-mode; remote-endpoint = <&etm1_out_port>; }; }; };