/* * Device Tree Source for the r8a73a4 SoC * * Copyright (C) 2013 Renesas Solutions Corp. * Copyright (C) 2013 Magnus Damm * * This file is licensed under the terms of the GNU General Public License * version 2. This program is licensed "as is" without any warranty of any * kind, whether express or implied. */ #include #include #include / { compatible = "renesas,r8a73a4"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1500000000>; power-domains = <&pd_a2sl>; }; }; ptm { compatible = "arm,coresight-etm3x"; power-domains = <&pd_d4>; }; timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; dbsc1: memory-controller@e6790000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe6790000 0 0x10000>; power-domains = <&pd_a3bc>; }; dbsc2: memory-controller@e67a0000 { compatible = "renesas,dbsc-r8a73a4"; reg = <0 0xe67a0000 0 0x10000>; power-domains = <&pd_a3bc>; }; dmac: dma-multiplexer { compatible = "renesas,shdma-mux"; #dma-cells = <1>; dma-channels = <20>; dma-requests = <256>; #address-cells = <2>; #size-cells = <2>; ranges; dma0: dma-controller@e6700020 { compatible = "renesas,shdma-r8a73a4"; reg = <0 0xe6700020 0 0x89e0>; interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH 0 200 IRQ_TYPE_LEVEL_HIGH 0 201 IRQ_TYPE_LEVEL_HIGH 0 202 IRQ_TYPE_LEVEL_HIGH 0 203 IRQ_TYPE_LEVEL_HIGH 0 204 IRQ_TYPE_LEVEL_HIGH 0 205 IRQ_TYPE_LEVEL_HIGH 0 206 IRQ_TYPE_LEVEL_HIGH 0 207 IRQ_TYPE_LEVEL_HIGH 0 208 IRQ_TYPE_LEVEL_HIGH 0 209 IRQ_TYPE_LEVEL_HIGH 0 210 IRQ_TYPE_LEVEL_HIGH 0 211 IRQ_TYPE_LEVEL_HIGH 0 212 IRQ_TYPE_LEVEL_HIGH 0 213 IRQ_TYPE_LEVEL_HIGH 0 214 IRQ_TYPE_LEVEL_HIGH 0 215 IRQ_TYPE_LEVEL_HIGH 0 216 IRQ_TYPE_LEVEL_HIGH 0 217 IRQ_TYPE_LEVEL_HIGH 0 218 IRQ_TYPE_LEVEL_HIGH 0 219 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19"; clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; power-domains = <&pd_a3sp>; }; }; i2c5: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x428>; interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; power-domains = <&pd_a3sp>; status = "disabled"; }; cmt1: timer@e6130000 { compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; reg = <0 0xe6130000 0 0x1004>; interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; clock-names = "fck"; power-domains = <&pd_c5>; renesas,channels-mask = <0xff>; status = "disabled"; }; irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, <0 1 IRQ_TYPE_LEVEL_HIGH>, <0 2 IRQ_TYPE_LEVEL_HIGH>, <0 3 IRQ_TYPE_LEVEL_HIGH>, <0 4 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>, <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 7 IRQ_TYPE_LEVEL_HIGH>, <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>, <0 10 IRQ_TYPE_LEVEL_HIGH>, <0 11 IRQ_TYPE_LEVEL_HIGH>, <0 12 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 14 IRQ_TYPE_LEVEL_HIGH>, <0 15 IRQ_TYPE_LEVEL_HIGH>, <0 16 IRQ_TYPE_LEVEL_HIGH>, <0 17 IRQ_TYPE_LEVEL_HIGH>, <0 18 IRQ_TYPE_LEVEL_HIGH>, <0 19 IRQ_TYPE_LEVEL_HIGH>, <0 20 IRQ_TYPE_LEVEL_HIGH>, <0 21 IRQ_TYPE_LEVEL_HIGH>, <0 22 IRQ_TYPE_LEVEL_HIGH>, <0 23 IRQ_TYPE_LEVEL_HIGH>, <0 24 IRQ_TYPE_LEVEL_HIGH>, <0 25 IRQ_TYPE_LEVEL_HIGH>, <0 26 IRQ_TYPE_LEVEL_HIGH>, <0 27 IRQ_TYPE_LEVEL_HIGH>, <0 28 IRQ_TYPE_LEVEL_HIGH>, <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>, <0 31 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_c4>; }; irqc1: interrupt-controller@e61c0200 { compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0200 0 0x200>; interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, <0 33 IRQ_TYPE_LEVEL_HIGH>, <0 34 IRQ_TYPE_LEVEL_HIGH>, <0 35 IRQ_TYPE_LEVEL_HIGH>, <0 36 IRQ_TYPE_LEVEL_HIGH>, <0 37 IRQ_TYPE_LEVEL_HIGH>, <0 38 IRQ_TYPE_LEVEL_HIGH>, <0 39 IRQ_TYPE_LEVEL_HIGH>, <0 40 IRQ_TYPE_LEVEL_HIGH>, <0 41 IRQ_TYPE_LEVEL_HIGH>, <0 42 IRQ_TYPE_LEVEL_HIGH>, <0 43 IRQ_TYPE_LEVEL_HIGH>, <0 44 IRQ_TYPE_LEVEL_HIGH>, <0 45 IRQ_TYPE_LEVEL_HIGH>, <0 46 IRQ_TYPE_LEVEL_HIGH>, <0 47 IRQ_TYPE_LEVEL_HIGH>, <0 48 IRQ_TYPE_LEVEL_HIGH>, <0 49 IRQ_TYPE_LEVEL_HIGH>, <0 50 IRQ_TYPE_LEVEL_HIGH>, <0 51 IRQ_TYPE_LEVEL_HIGH>, <0 52 IRQ_TYPE_LEVEL_HIGH>, <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 55 IRQ_TYPE_LEVEL_HIGH>, <0 56 IRQ_TYPE_LEVEL_HIGH>, <0 57 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_c4>; }; pfc: pfc@e6050000 { compatible = "renesas,pfc-r8a73a4"; reg = <0 0xe6050000 0 0x9000>; gpio-controller; #gpio-cells = <2>; interrupts-extended = <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, <&irqc1 24 0>, <&irqc1 25 0>; power-domains = <&pd_c5>; }; thermal@e61f0000 { compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; power-domains = <&pd_c5>; }; i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c1: i2c@e6510000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c2: i2c@e6520000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c3: i2c@e6530000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c4: i2c@e6540000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c6: i2c@e6550000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c7: i2c@e6560000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; power-domains = <&pd_a3sp>; status = "disabled"; }; i2c8: i2c@e6570000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; power-domains = <&pd_a3sp>; status = "disabled"; }; scifb0: serial@e6c20000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; status = "disabled"; }; scifb1: serial@e6c30000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; status = "disabled"; }; scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c40000 0 0x100>; interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; status = "disabled"; }; scifa1: serial@e6c50000 { compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c50000 0 0x100>; interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; status = "disabled"; }; scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; clock-names = "sci_ick"; power-domains = <&pd_a3sp>; status = "disabled"; }; scifb3: serial@e6cf0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6cf0000 0 0x100>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; clock-names = "sci_ick"; power-domains = <&pd_c4>; status = "disabled"; }; sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee120000 0 0x100>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; power-domains = <&pd_a3sp>; cap-sd-highspeed; status = "disabled"; }; mmcif0: mmc@ee200000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; mmcif1: mmc@ee220000 { compatible = "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; power-domains = <&pd_a3sp>; reg-io-width = <4>; status = "disabled"; }; gic: interrupt-controller@f1001000 { compatible = "arm,cortex-a15-gic"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x1000>, <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; bsc: bus@fec10000 { compatible = "renesas,bsc-r8a73a4", "renesas,bsc", "simple-pm-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0x20000000>; reg = <0 0xfec10000 0 0x400>; clocks = <&zb_clk>; power-domains = <&pd_c4>; }; clocks { #address-cells = <2>; #size-cells = <2>; ranges; /* External root clocks */ extalr_clk: extalr_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; clock-output-names = "extalr"; }; extal1_clk: extal1_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; clock-output-names = "extal1"; }; extal2_clk: extal2_clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; clock-output-names = "extal2"; }; fsiack_clk: fsiack_clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; clock-output-names = "fsiack"; }; fsibck_clk: fsibck_clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; clock-output-names = "fsibck"; }; /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a73a4-cpg-clocks"; reg = <0 0xe6150000 0 0x10000>; clocks = <&extal1_clk>, <&extal2_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", "zx", "zs", "hp"; }; /* Variable factor clocks (DIV6) */ zb_clk: zb_clk@e6150010 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150010 0 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; #clock-cells = <0>; clock-output-names = "zb"; }; sdhi0_clk: sdhi0_clk@e6150074 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150074 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "sdhi0ck"; }; sdhi1_clk: sdhi1_clk@e6150078 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "sdhi1ck"; }; sdhi2_clk: sdhi2_clk@e615007c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615007c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "sdhi2ck"; }; mmc0_clk: mmc0_clk@e6150240 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "mmc0"; }; mmc1_clk: mmc1_clk@e6150244 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150244 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "mmc1"; }; vclk1_clk: vclk1_clk@e6150008 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150008 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; clock-output-names = "vclk1"; }; vclk2_clk: vclk2_clk@e615000c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615000c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; clock-output-names = "vclk2"; }; vclk3_clk: vclk3_clk@e615001c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615001c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; clock-output-names = "vclk3"; }; vclk4_clk: vclk4_clk@e6150014 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150014 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; clock-output-names = "vclk4"; }; vclk5_clk: vclk5_clk@e6150034 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150034 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; clock-output-names = "vclk5"; }; fsia_clk: fsia_clk@e6150018 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150018 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&fsiack_clk>, <0>; #clock-cells = <0>; clock-output-names = "fsia"; }; fsib_clk: fsib_clk@e6150090 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150090 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&fsibck_clk>, <0>; #clock-cells = <0>; clock-output-names = "fsib"; }; mp_clk: mp_clk@e6150080 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150080 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "mp"; }; m4_clk: m4_clk@e6150098 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150098 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; #clock-cells = <0>; clock-output-names = "m4"; }; hsi_clk: hsi_clk@e615026c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; #clock-cells = <0>; clock-output-names = "hsi"; }; spuv_clk: spuv_clk@e6150094 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150094 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; clock-output-names = "spuv"; }; /* Fixed factor clocks */ main_div2_clk: main_div2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "main_div2"; }; pll0_div2_clk: pll0_div2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "pll0_div2"; }; pll1_div2_clk: pll1_div2_clk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "pll1_div2"; }; extal1_div2_clk: extal1_div2_clk { compatible = "fixed-factor-clock"; clocks = <&extal1_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; clock-output-names = "extal1_div2"; }; /* Gate clocks */ mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 R8A73A4_CLK_DMAC >; clock-output-names = "scifa0", "scifa1", "scifb0", "scifb1", "scifb2", "scifb3", "dmac"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>, <&extalr_clk>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 R8A73A4_CLK_CMT1 >; clock-output-names = "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "iic6", "iic7", "iic0", "iic1", "cmt1"; }; mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 >; clock-output-names = "iic5", "iic4", "iic3"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 >; clock-output-names = "thermal", "iic8"; }; }; sysc: system-controller@e6180000 { compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; pm-domains { pd_c5: c5 { #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_c4: c4@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a3sg: a3sg@16 { reg = <16>; #power-domain-cells = <0>; }; pd_a3ex: a3ex@17 { reg = <17>; #power-domain-cells = <0>; }; pd_a3sp: a3sp@18 { reg = <18>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a2us: a2us@19 { reg = <19>; #power-domain-cells = <0>; }; }; pd_a3sm: a3sm@20 { reg = <20>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a2sl: a2sl@21 { reg = <21>; #power-domain-cells = <0>; }; }; pd_a3km: a3km@22 { reg = <22>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a2kl: a2kl@23 { reg = <23>; #power-domain-cells = <0>; }; }; }; pd_c4ma: c4ma@1 { reg = <1>; #power-domain-cells = <0>; }; pd_c4cl: c4cl@2 { reg = <2>; #power-domain-cells = <0>; }; pd_d4: d4@3 { reg = <3>; #power-domain-cells = <0>; }; pd_a4bc: a4bc@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a3bc: a3bc@5 { reg = <5>; #power-domain-cells = <0>; }; }; pd_a4l: a4l@6 { reg = <6>; #power-domain-cells = <0>; }; pd_a4lc: a4lc@7 { reg = <7>; #power-domain-cells = <0>; }; pd_a4mp: a4mp@8 { reg = <8>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a3mp: a3mp@9 { reg = <9>; #power-domain-cells = <0>; }; pd_a3vc: a3vc@10 { reg = <10>; #power-domain-cells = <0>; }; }; pd_a4sf: a4sf@11 { reg = <11>; #power-domain-cells = <0>; }; pd_a3r: a3r@12 { reg = <12>; #address-cells = <1>; #size-cells = <0>; #power-domain-cells = <0>; pd_a2rv: a2rv@13 { reg = <13>; #power-domain-cells = <0>; }; pd_a2is: a2is@14 { reg = <14>; #power-domain-cells = <0>; }; }; }; }; }; };