/*
 * arch/arm/boot/dts/tegra124-vcm30_t124.dts
 *
 * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 *
 */

 /dts-v1/;

#include "tegra124.dtsi"
#include <tegra124-platforms/tegra124-vcm30-t124-gpio-default.dtsi>
#include <tegra124-platforms/tegra124-vcm30-t124-pinmux.dtsi>


/ {
	model = "NVIDIA Tegra124 vcm30t124";
	compatible = "nvidia,vcm30t124", "nvidia,tegra124";
	nvidia,dtsfilename = __FILE__;
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		nvidia,tegra-hypervisor-mode;
	};

	i2c@7000c400 {
		nvidia,clock-always-on;
	};

        serial@70006000 {
                compatible = "nvidia,tegra114-hsuart";
                status = "okay";
        };

        serial@70006040 {
                compatible = "nvidia,tegra114-hsuart";
                status = "okay";
        };

        serial@70006300 {
                compatible = "nvidia,tegra114-hsuart";
                status = "okay";
        };

	spi@7000d400 {
		status = "okay";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
			/* spi-cpha;
			 * spi-cpol;
			 * spi-cs-high;
			 */
		};
	};

	spi@7000d600 {
		status = "okay";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
		};
	};

	spi@7000d800 {
		status = "okay";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
		};
	};

	spi@7000dc00 {
		status = "okay";
		spi@0 {
			compatible = "spidev";
			reg = <0>;
			spi-max-frequency = <25000000>;
		};
	};

	ahub {
		status = "okay";

		i2s@70301000 {
			status = "okay";
		};
		i2s@70301400 {
			status = "okay";
		};
		spdif@70306000 {
			status = "okay";
		};
		amx@70303000 {
			status = "okay";
		};
		adx@70303800 {
			status = "okay";
		};
		amx@70303100 {
			status = "okay";
		};
		adx@70303900 {
			status = "okay";
		};
		dam@70302000 {
			status = "okay";
		};
		dam@70302200 {
			status = "okay";
		};
		dam@70302400 {
			status = "okay";
		};
		afc@70307000 {
			status = "okay";
		};
		afc@70307100 {
			status = "okay";
		};
		afc@70307200 {
			status = "okay";
		};
		afc@70307300 {
			status = "okay";
		};
		afc@70307400 {
			status = "okay";
		};
		afc@70307500 {
			status = "okay";
		};
	};

	pcie-controller {
		nvidia,port0_status = <1>;
		nvidia,port1_status = <1>;
		status = "okay";
	};

	sata@0x70020000 {
		status = "okay";
		nvidia,enable-sata-port;
	};

	sdhci@700b0600 {
		tap-delay = <0x4>;
		trim-delay = <0x4>;
		ddr-trim-delay = <0x4>;
		mmc-ocr-mask = <0>;
		uhs_mask = <0x40>;
		bus-width = <8>;
		built-in;
		ddr-clk-limit = <51000000>;
		max-clk-limit = <200000000>;
		status = "okay";
	};

	sdhci@700b0200 {
		tap-delay = <0x1>;
		trim-delay = <0x3>;
		ddr-trim-delay = <0x3>;
		mmc-ocr-mask = <0>;
		uhs_mask = <0x20>;
		built-in;
		ddr-clk-limit = <30000000>;
		max-clk-limit = <51000000>;
		status = "okay";
	};

	sdhci@700b0400 {
		cd-gpios = <&gpio 133 0>;
		wp-gpios = <&gpio 132 0>;
		tap-delay = <0>;
		trim-delay = <3>;
		mmc-ocr-mask = <3>;
		uhs_mask = <0x2F>;
		bus-width = <4>;
		max-clk-limit = <50000000>;
		status = "okay";
	};

/* All ardbeg devices are using ttyTHS2 port for BT.
 * So changed the enumerated ordering of uartd from ttyTHS3 to ttyTHS2
 */
	aliases {
		i2c0 = &i2c1;
		i2c1 = &i2c2;
		i2c2 = &i2c3;
		i2c3 = &i2c4;
		i2c4 = &i2c5;
		i2c5 = &i2c6;
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartd;
		serial3 = &uartc;
		spi0 = &spi0;
		spi1 = &spi1;
		spi2 = &spi2;
		spi3 = &spi3;
		spi4 = &spi4;
		spi5 = &spi5;
	};
};