/* * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iomux.h" #include "mx53_pins.h" #include "crm_regs.h" #include "devices.h" #include "usb.h" /*! * @file mach-mx53/mx53_evk.c * * @brief This file contains the board specific initialization routines. * * @ingroup MSL_MX53 */ extern int __init mx53_evk_init_mc13892(void); extern void __init mx53_evk_io_init(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); static int num_cpu_wp = 3; /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ static struct cpu_wp cpu_wp_auto[] = { { .pll_rate = 1000000000, .cpu_rate = 1000000000, .pdf = 0, .mfi = 10, .mfd = 11, .mfn = 5, .cpu_podf = 0, .cpu_voltage = 1150000,}, { .pll_rate = 800000000, .cpu_rate = 800000000, .pdf = 0, .mfi = 8, .mfd = 2, .mfn = 1, .cpu_podf = 0, .cpu_voltage = 1050000,}, { .pll_rate = 800000000, .cpu_rate = 160000000, .pdf = 4, .mfi = 8, .mfd = 2, .mfn = 1, .cpu_podf = 4, .cpu_voltage = 850000,}, }; static struct fb_videomode video_modes[] = { { /* NTSC TV output */ "TV-NTSC", 60, 720, 480, 74074, 122, 15, 18, 26, 1, 1, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, FB_VMODE_INTERLACED, 0,}, { /* PAL TV output */ "TV-PAL", 50, 720, 576, 74074, 132, 11, 22, 26, 1, 1, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, 0,}, { "720P60", 60, 1280, 720, 13468, 260, 109, 25, 4, 1, 1, FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, FB_VMODE_NONINTERLACED, 0,}, { /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, FB_SYNC_CLK_LAT_FALL, FB_VMODE_NONINTERLACED, 0,}, { /* 1600x1200 @ 60 Hz 162M pixel clk*/ "UXGA", 60, 1600, 1200, 6172, 304, 64, 1, 46, 192, 3, FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, FB_VMODE_NONINTERLACED, 0,}, { "1080P60", 60, 1920, 1080, 7692, 100, 40, 30, 3, 10, 2, FB_SYNC_EXT, FB_VMODE_NONINTERLACED, 0,}, { "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10, FB_SYNC_EXT, FB_VMODE_NONINTERLACED, 0,}, }; struct cpu_wp *mx53_evk_get_cpu_wp(int *wp) { *wp = num_cpu_wp; return cpu_wp_auto; } void mx53_evk_set_num_cpu_wp(int num) { num_cpu_wp = num; return; } static struct mxc_w1_config mxc_w1_data = { .search_rom_accelerator = 1, }; static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 1, .max_brightness = 255, .dft_brightness = 128, .pwm_period_ns = 78770, }; extern void flexcan_xcvr_enable(int id, int en); static struct flexcan_platform_data flexcan0_data = { .core_reg = NULL, .io_reg = NULL, .xcvr_enable = flexcan_xcvr_enable, .br_clksrc = 1, .br_rjw = 2, .br_presdiv = 5, .br_propseg = 5, .br_pseg1 = 4, .br_pseg2 = 7, .bcc = 1, .srx_dis = 1, .smp = 1, .boff_rec = 1, .ext_msg = 1, .std_msg = 1, }; static struct flexcan_platform_data flexcan1_data = { .core_reg = NULL, .io_reg = NULL, .xcvr_enable = flexcan_xcvr_enable, .br_clksrc = 1, .br_rjw = 2, .br_presdiv = 5, .br_propseg = 5, .br_pseg1 = 4, .br_pseg2 = 7, .bcc = 1, .srx_dis = 1, .boff_rec = 1, .ext_msg = 1, .std_msg = 1, }; extern void mx5_ipu_reset(void); static struct mxc_ipu_config mxc_ipu_data = { .rev = 3, .reset = mx5_ipu_reset, }; extern void mx5_vpu_reset(void); static struct mxc_vpu_platform_data mxc_vpu_data = { .reset = mx5_vpu_reset, }; static struct fec_platform_data fec_data = { .phy = PHY_INTERFACE_MODE_RMII, }; extern void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, int chipselect); extern void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, int chipselect); static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, .chipselect_active = mx53_evk_gpio_spi_chipselect_active, .chipselect_inactive = mx53_evk_gpio_spi_chipselect_inactive, }; static struct mxc_i2c_platform_data mxci2c_data = { .i2c_clk = 100000, }; static struct mxc_srtc_platform_data srtc_data = { .srtc_sec_mode_addr = 0x83F98840, }; static struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", .gpc_cntr_reg_addr = MXC_GPC_CNTR, .gpc_vcr_reg_addr = MXC_GPC_VCR, .ccm_cdcr_reg_addr = MXC_CCM_CDCR, .ccm_cacrr_reg_addr = MXC_CCM_CACRR, .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, .div3ck_mask = 0xE0000000, .div3ck_offset = 29, .div3ck_val = 2, .emac_val = 0x08, .upthr_val = 25, .dnthr_val = 9, .pncthr_val = 33, .upcnt_val = 10, .dncnt_val = 10, .delay_time = 30, .num_wp = 3, }; static struct tve_platform_data tve_data = { .dac_reg = "VVIDEO", }; static struct ldb_platform_data ldb_data = { .lvds_bg_reg = "VAUDIO", .ext_ref = 1, }; static struct mxc_esai_platform_data esai_data = { .activate_esai_ports = gpio_activate_esai_ports, }; static void adv7180_pwdn(int pwdn) { gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); if (pwdn) gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); else gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 1); } static struct mxc_tvin_platform_data adv7180_data = { .dvddio_reg = NULL, .dvdd_reg = NULL, .avdd_reg = NULL, .pvdd_reg = NULL, .pwdn = adv7180_pwdn, .reset = NULL, }; static struct resource mxcfb_resources[] = { [0] = { .flags = IORESOURCE_MEM, }, }; static struct mxc_fb_platform_data fb_data[] = { { .interface_pix_fmt = IPU_PIX_FMT_RGB565, .mode_str = "CLAA-WVGA", .mode = video_modes, .num_modes = ARRAY_SIZE(video_modes), }, { .interface_pix_fmt = IPU_PIX_FMT_BGR24, .mode_str = "1024x768M-16@60", .mode = video_modes, .num_modes = ARRAY_SIZE(video_modes), }, }; extern int primary_di; static int __init mxc_init_fb(void) { if (!machine_is_mx53_evk()) return 0; if (primary_di) { printk(KERN_INFO "DI1 is primary\n"); /* DI1 -> DP-BG channel: */ mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); mxc_fb_devices[1].resource = mxcfb_resources; mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); /* DI0 -> DC channel: */ mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); } else { printk(KERN_INFO "DI0 is primary\n"); /* DI0 -> DP-BG channel: */ mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); mxc_fb_devices[0].resource = mxcfb_resources; mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); /* DI1 -> DC channel: */ mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); } /* * DI0/1 DP-FG channel: */ mxc_register_device(&mxc_fb_devices[2], NULL); return 0; } device_initcall(mxc_init_fb); static void camera_pwdn(int pwdn) { gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), pwdn); } static struct mxc_camera_platform_data camera_data = { .analog_regulator = "VSD", .mclk = 24000000, .csi = 0, .pwdn = camera_pwdn, }; static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { { .type = "ov3640", .addr = 0x3C, .platform_data = (void *)&camera_data, }, { .type = "adv7180", .addr = 0x21, .platform_data = (void *)&adv7180_data, }, { .type = "cs42888", .addr = 0x48, }, }; /* TO DO add platform data */ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { .type = "sgtl5000-i2c", .addr = 0x0a, }, { .type = "tsc2007", .addr = 0x48, .irq = IOMUX_TO_IRQ(MX53_PIN_EIM_A25), }, { .type = "backlight-i2c", .addr = 0x2c, }, { .type = "vga-ddc", .addr = 0x1f, }, { .type = "eeprom", .addr = 0x50, }, }; static struct mtd_partition mxc_dataflash_partitions[] = { { .name = "bootloader", .offset = 0, .size = 0x000100000,}, { .name = "kernel", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL,}, }; static struct flash_platform_data mxc_spi_flash_data[] = { { .name = "mxc_dataflash", .parts = mxc_dataflash_partitions, .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), .type = "at45db321d",} }; static struct spi_board_info mxc_dataflash_device[] __initdata = { { .modalias = "mxc_dataflash", .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ .bus_num = 1, .chip_select = 1, .platform_data = &mxc_spi_flash_data[0],}, }; static int sdhc_write_protect(struct device *dev) { unsigned short rc = 0; if (!board_is_mx53_arm2()) { if (to_platform_device(dev)->id == 0) rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14)); else rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12)); } return rc; } static unsigned int sdhc_get_card_det_status(struct device *dev) { int ret; if (board_is_mx53_arm2()) { if (to_platform_device(dev)->id == 0) ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); else ret = 1; } else { if (to_platform_device(dev)->id == 0) { ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); } else{ /* config the det pin for SDHC3 */ ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11)); } } return ret; } static struct mxc_mmc_platform_data mmc1_data = { .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_31_32, .caps = MMC_CAP_4_BIT_DATA, .min_clk = 400000, .max_clk = 50000000, .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", .power_mmc = NULL, }; static struct mxc_mmc_platform_data mmc3_data = { .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_31_32, .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR, .min_clk = 400000, .max_clk = 50000000, .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", }; /* return value 1 failure, 0 success */ static int write_phy_ctl_ack_polling(u32 data, void __iomem *mmio, int max_iterations, u32 exp_val) { enum { PORT_PHY_CTL = 0x178, /* Port0 PHY Control */ PORT_PHY_SR = 0x17c, /* Port0 PHY Status */ /* PORT_PHY_SR */ PORT_PHY_STAT_DATA_LOC = 0, PORT_PHY_STAT_ACK_LOC = 18, }; int i; u32 val; writel(data, mmio + PORT_PHY_CTL); for (i = 0; i < max_iterations + 1; i++) { val = readl(mmio + PORT_PHY_SR); val = (val >> PORT_PHY_STAT_ACK_LOC) & 0x1; if (val == exp_val) return 0; if (i == max_iterations) { printk(KERN_ERR "Wait for CR ACK error!\n"); return 1; } msleep(1); } return 0; } /* HW Initialization, if return 1, initialization is failed. */ static int sata_init(struct device *dev) { enum { HOST_CAP = 0x00, HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ HOST_PORTS_IMPL = 0x0c, HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ /* Offest used to control the MPLL input clk */ PHY_CR_CLOCK_FREQ_OVRD = 0x12, PORT_PHY_CTL = 0x178, /* Port0 PHY Control */ /* PORT_PHY_CTL bits */ PORT_PHY_CTL_CAP_ADR_LOC = 0x10000, PORT_PHY_CTL_CAP_DAT_LOC = 0x20000, PORT_PHY_CTL_WRITE_LOC = 0x40000, }; void __iomem *mmio; struct clk *clk; int rc = 0; u32 tmpdata; clk = clk_get(dev, "sata_clk"); clk_enable(clk); mmio = ioremap(MX53_SATA_BASE_ADDR, SZ_4K); tmpdata = readl(mmio + HOST_CAP); if (!(tmpdata & HOST_CAP_SSS)) { tmpdata |= HOST_CAP_SSS; writel(tmpdata, mmio + HOST_CAP); } if (!(readl(mmio + HOST_PORTS_IMPL) & 0x1)) writel((readl(mmio + HOST_PORTS_IMPL) | 0x1), mmio + HOST_PORTS_IMPL); /* Get the AHB clock rate, and configure the TIMER1MS reg */ clk = clk_get(NULL, "ahb_clk"); tmpdata = clk_get_rate(clk) / 1000; writel(tmpdata, mmio + HOST_TIMER1MS); /* write addr */ tmpdata = PHY_CR_CLOCK_FREQ_OVRD; writel(tmpdata, mmio + PORT_PHY_CTL); /* capture addr */ tmpdata |= PORT_PHY_CTL_CAP_ADR_LOC; /* Wait for ack */ if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 1)) { rc = 1; goto err0; } /* deassert cap data */ tmpdata &= 0xFFFF; /* wait for ack de-assertion */ if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 0)) { rc = 1; goto err0; } /* write data */ /* Configure the PHY CLK input refer to different OSC * For 25MHz, pre[13,14]:01, ncy[12,8]:06, * ncy5[7,6]:02, int_ctl[5,3]:0, prop_ctl[2,0]:7. * For 50MHz, pre:00, ncy:06, ncy5:02, int_ctl:0, prop_ctl:7. */ /* EVK revA */ if (board_is_mx53_evk_a()) tmpdata = (0x1 << 15) | (0x1 << 13) | (0x6 << 8) | (0x2 << 6) | 0x7; /* EVK revB */ else if (board_is_mx53_evk_b()) tmpdata = (0x1 << 15) | (0x0 << 13) | (0x6 << 8) | (0x2 << 6) | 0x7; writel(tmpdata, mmio + PORT_PHY_CTL); /* capture data */ tmpdata |= PORT_PHY_CTL_CAP_DAT_LOC; /* wait for ack */ if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 1)) { rc = 1; goto err0; } /* deassert cap data */ tmpdata &= 0xFFFF; /* wait for ack de-assertion */ if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 0)) { rc = 1; goto err0; } /* assert wr signal and wait for ack */ if (write_phy_ctl_ack_polling(PORT_PHY_CTL_WRITE_LOC, mmio, 100, 1)) { rc = 1; goto err0; } /* deassert rd _signal and wait for ack de-assertion */ if (write_phy_ctl_ack_polling(0, mmio, 100, 0)) { rc = 1; goto err0; } msleep(10); err0: iounmap(mmio); return rc; } static void sata_exit(struct device *dev) { struct clk *clk; clk = clk_get(dev, "sata_clk"); clk_disable(clk); clk_put(clk); } static struct ahci_platform_data sata_data = { .init = sata_init, .exit = sata_exit, }; static int mxc_sgtl5000_amp_enable(int enable) { /* TO DO */ return 0; } static int headphone_det_status(void) { return (gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)) == 0); } static int mxc_sgtl5000_init(void); static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 5, .hp_irq = IOMUX_TO_IRQ(MX53_PIN_ATA_DATA5), .hp_status = headphone_det_status, .amp_enable = mxc_sgtl5000_amp_enable, .init = mxc_sgtl5000_init, }; static int mxc_sgtl5000_init(void) { struct clk *ssi_ext1; int rate; if (board_is_mx53_arm2()) { sgtl5000_data.sysclk = 12000000; } else { ssi_ext1 = clk_get(NULL, "ssi_ext1_clk"); if (IS_ERR(ssi_ext1)) return -1; rate = clk_round_rate(ssi_ext1, 24000000); if (rate < 8000000 || rate > 27000000) { printk(KERN_ERR "Error: SGTL5000 mclk freq %d out of range!\n", rate); clk_put(ssi_ext1); return -1; } clk_set_rate(ssi_ext1, rate); clk_enable(ssi_ext1); sgtl5000_data.sysclk = rate; } return 0; } static struct platform_device mxc_sgtl5000_device = { .name = "imx-3stack-sgtl5000", }; static struct mxc_mlb_platform_data mlb_data = { .reg_nvcc = "VCAM", .mlb_clk = "mlb_clk", }; /* NAND Flash Partitions */ #ifdef CONFIG_MTD_PARTITIONS static struct mtd_partition nand_flash_partitions[] = { { .name = "bootloader", .offset = 0, .size = 3 * 1024 * 1024}, { .name = "nand.kernel", .offset = MTDPART_OFS_APPEND, .size = 5 * 1024 * 1024}, { .name = "nand.rootfs", .offset = MTDPART_OFS_APPEND, .size = 256 * 1024 * 1024}, { .name = "nand.userfs1", .offset = MTDPART_OFS_APPEND, .size = 256 * 1024 * 1024}, { .name = "nand.userfs2", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL}, }; #endif static int nand_init(void) { u32 i, reg; void __iomem *base; #define M4IF_GENP_WEIM_MM_MASK 0x00000001 #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); reg = __raw_readl(base + 0xc); reg &= ~M4IF_GENP_WEIM_MM_MASK; __raw_writel(reg, base + 0xc); iounmap(base); base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K); for (i = 0x4; i < 0x94; i += 0x18) { reg = __raw_readl((u32)base + i); reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; __raw_writel(reg, (u32)base + i); } iounmap(base); return 0; } static struct flash_platform_data mxc_nand_data = { #ifdef CONFIG_MTD_PARTITIONS .parts = nand_flash_partitions, .nr_parts = ARRAY_SIZE(nand_flash_partitions), #endif .width = 1, .init = nand_init, }; static struct mxc_spdif_platform_data mxc_spdif_data = { .spdif_tx = 1, .spdif_rx = 0, .spdif_clk_44100 = 0, /* Souce from CKIH1 for 44.1K */ .spdif_clk_48000 = 7, /* Source from CKIH2 for 48k and 32k */ .spdif_clkid = 0, .spdif_clk = NULL, /* spdif bus clk */ }; static struct mxc_audio_platform_data mxc_surround_audio_data = { .ext_ram = 1, }; static struct platform_device mxc_alsa_surround_device = { .name = "imx-3stack-cs42888", }; static int __initdata mxc_apc_on = { 0 }; /* OFF: 0 (default), ON: 1 */ static int __init apc_setup(char *__unused) { mxc_apc_on = 1; printk(KERN_INFO "Automotive Port Card is Plugged on\n"); return 1; } __setup("apc", apc_setup); /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to * statically fill in the proper values for the passed-in parameters. None of * the parameters is used currently. * * @param desc pointer to \b struct \b machine_desc * @param tags pointer to \b struct \b tag * @param cmdline pointer to the command line * @param mi pointer to \b struct \b meminfo */ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { struct tag *t; struct tag *mem_tag = 0; int total_mem = SZ_1G; int left_mem = 0; int gpu_mem = SZ_128M; int fb_mem = SZ_32M; char *str; mxc_set_cpu_type(MXC_CPU_MX53); get_cpu_wp = mx53_evk_get_cpu_wp; set_num_cpu_wp = mx53_evk_set_num_cpu_wp; for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; left_mem = total_mem - gpu_mem - fb_mem; break; } } for_each_tag(t, tags) { if (t->hdr.tag == ATAG_CMDLINE) { str = t->u.cmdline.cmdline; str = strstr(str, "mem="); if (str != NULL) { str += 4; left_mem = memparse(str, &str); if (left_mem == 0 || left_mem > total_mem) left_mem = total_mem - gpu_mem - fb_mem; } str = t->u.cmdline.cmdline; str = strstr(str, "gpu_memory="); if (str != NULL) { str += 11; gpu_mem = memparse(str, &str); } break; } } if (mem_tag) { fb_mem = total_mem - left_mem - gpu_mem; if (fb_mem < 0) { gpu_mem = total_mem - left_mem; fb_mem = 0; } mem_tag->u.mem.size = left_mem; /*reserve memory for gpu*/ gpu_device.resource[5].start = mem_tag->u.mem.start + left_mem; gpu_device.resource[5].end = gpu_device.resource[5].start + gpu_mem - 1; #if defined(CONFIG_FB_MXC_SYNC_PANEL) || \ defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) if (fb_mem) { mxcfb_resources[0].start = gpu_device.resource[5].end + 1; mxcfb_resources[0].end = mxcfb_resources[0].start + fb_mem - 1; } else { mxcfb_resources[0].start = 0; mxcfb_resources[0].end = 0; } #endif } } extern void mx53_gpio_usbotg_driver_vbus(bool on); extern void mx53_gpio_host1_driver_vbus(bool on); /*! * Board specific initialization. */ static void __init mxc_board_init(void) { mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); clk_put(mxc_spdif_data.spdif_core_clk); /* SD card detect irqs */ if (board_is_mx53_arm2()) { mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_GPIO_1); mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_GPIO_1); mmc3_data.card_inserted_state = 1; mmc3_data.status = NULL; mmc3_data.wp_status = NULL; mmc1_data.wp_status = NULL; } else { mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); } mxc_cpu_common_init(); mxc_register_gpios(); mx53_evk_io_init(); mxc_register_device(&mxc_dma_device, NULL); mxc_register_device(&mxc_wdt_device, NULL); mxc_register_device(&mxcspi1_device, &mxcspi1_data); mxc_register_device(&mxci2c_devices[0], &mxci2c_data); mxc_register_device(&mxci2c_devices[1], &mxci2c_data); mxc_register_device(&mxci2c_devices[2], &mxci2c_data); mxc_register_device(&mxc_rtc_device, &srtc_data); mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); mxc_register_device(&mxc_ldb_device, &ldb_data); mxc_register_device(&mxc_tve_device, &tve_data); mxc_register_device(&mxcvpu_device, &mxc_vpu_data); mxc_register_device(&gpu_device, NULL); mxc_register_device(&mxcscc_device, NULL); /* mxc_register_device(&mx53_lpmode_device, NULL); mxc_register_device(&busfreq_device, NULL); mxc_register_device(&sdram_autogating_device, NULL); */ mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); mxc_register_device(&busfreq_device, NULL); /* mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); */ mxc_register_device(&mxc_iim_device, NULL); if (!board_is_mx53_arm2()) { mxc_register_device(&mxc_pwm2_device, NULL); mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); } mxc_register_device(&mxc_flexcan0_device, &flexcan0_data); mxc_register_device(&mxc_flexcan1_device, &flexcan1_data); /* mxc_register_device(&mxc_keypad_device, &keypad_plat_data); */ mxc_register_device(&mxcsdhc1_device, &mmc1_data); mxc_register_device(&mxcsdhc3_device, &mmc3_data); mxc_register_device(&mxc_ssi1_device, NULL); mxc_register_device(&mxc_ssi2_device, NULL); mxc_register_device(&ahci_fsl_device, &sata_data); mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); if (!mxc_apc_on) mxc_register_device(&mxc_fec_device, &fec_data); spi_register_board_info(mxc_dataflash_device, ARRAY_SIZE(mxc_dataflash_device)); i2c_register_board_info(0, mxc_i2c0_board_info, ARRAY_SIZE(mxc_i2c0_board_info)); i2c_register_board_info(1, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); mx53_evk_init_mc13892(); /* pm_power_off = mxc_power_off; */ mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); mxc_register_device(&mxc_mlb_device, &mlb_data); mx5_set_otghost_vbus_func(mx53_gpio_usbotg_driver_vbus); mx5_usb_dr_init(); mx5_set_host1_vbus_func(mx53_gpio_host1_driver_vbus); mx5_usbh1_init(); mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); if (mxc_apc_on) { mxc_register_device(&mxc_esai_device, &esai_data); mxc_register_device(&mxc_alsa_surround_device, &mxc_surround_audio_data); } } static void __init mx53_evk_timer_init(void) { struct clk *uart_clk; mx53_clocks_init(32768, 24000000, 22579200, 24576000); uart_clk = clk_get(NULL, "uart_clk.0"); early_console_setup(MX53_BASE_ADDR(UART1_BASE_ADDR), uart_clk); } static struct sys_timer mxc_timer = { .init = mx53_evk_timer_init, }; /* * The following uses standard kernel macros define in arch.h in order to * initialize __mach_desc_MX53_EVK data structure. */ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board") /* Maintainer: Freescale Semiconductor, Inc. */ .fixup = fixup_mxc_board, .map_io = mx5_map_io, .init_irq = mx5_init_irq, .init_machine = mxc_board_init, .timer = &mxc_timer, MACHINE_END