# Copyright (c) 2012-2014, NVIDIA CORPORATION. All rights reserved.
#
# This program is free software; you can redistribute it and/or modify it
# under the terms and conditions of the GNU General Public License,
# version 2, as published by the Free Software Foundation.
#
# This program is distributed in the hope it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
# more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see .
if ARCH_TEGRA
comment "NVIDIA Tegra options"
config ARCH_TEGRA_2x_SOC
bool "Enable support for Tegra20 family"
depends on !ARCH_TEGRA_12x_SOC
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_742230 if SMP
select ARM_ERRATA_751472
select ARM_ERRATA_754327 if SMP
select ARM_ERRATA_761320 if SMP
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select COMMON_CLK
select CPU_FREQ_TABLE if CPU_FREQ
select CPU_V7
select PINCTRL
select PINCTRL_TEGRA20
select PL310_ERRATA_727915 if CACHE_L2X0
select PL310_ERRATA_769419 if CACHE_L2X0
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_PHY
select USB_ULPI_VIEWPORT if USB_PHY
help
Support for NVIDIA Tegra AP20 and T20 processors, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_3x_SOC
bool "Enable support for Tegra30 family"
depends on !ARCH_TEGRA_12x_SOC
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select ARM_ERRATA_754322
select ARM_ERRATA_761320 if SMP
select ARM_ERRATA_764369 if SMP
select ARM_GIC
select COMMON_CLK
select CPU_FREQ_TABLE if CPU_FREQ
select CPU_V7
select PINCTRL
select PINCTRL_TEGRA30
select PL310_ERRATA_727915
select PL310_ERRATA_769419 if CACHE_L2X0
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB_PHY
select USB_ULPI_VIEWPORT if USB_PHY
help
Support for NVIDIA Tegra T30 processor family, based on the
ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
config ARCH_TEGRA_12x_SOC
bool "Tegra 12x family SOC"
select ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS if !ARM64
select ARCH_TEGRA_HAS_PCIE
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARM_ARCH_TIMER
select ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
select ARM_CPU_SUSPEND if PM
select ARM_SAVE_DEBUG_CONTEXT if PM_SLEEP
select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
select ARM_GIC
select ARCH_REQUIRE_GPIOLIB
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_EHCI_TEGRA if USB_SUPPORT
select USB_ULPI if USB_SUPPORT
select USB_ULPI_VIEWPORT if USB_SUPPORT
select USE_OF
select REPORT_PRESENT_CPUS if TEGRA_AUTO_HOTPLUG
select TEGRA_LP2_CPU_TIMER if !TEGRA_RAIL_OFF_MULTIPLE_CPUS
select ARCH_SUPPORTS_MSI if PCI_TEGRA
select PCI_MSI if PCI_TEGRA
select NVMAP_CACHE_MAINT_BY_SET_WAYS if TEGRA_NVMAP && !ARM64
select NVMAP_CACHE_MAINT_BY_SET_WAYS_ON_ONE_CPU if TEGRA_NVMAP && !ARM64
select ARCH_TEGRA_HAS_CL_DVFS
select TEGRA_DUAL_CBUS
select SOC_BUS
select THERMAL
select PM_GENERIC_DOMAINS if PM
select PINCTRL
select PINCTRL_TEGRA124
select POWER_RESET
select SYSTEM_PMIC
select TEGRA_DC_TEMPORAL_DITHER
select TEGRA_VDD_CORE_OVERRIDE if TEGRA_EMC_SCALING_ENABLE
select REGULATOR_TEGRA_DFLL_BYPASS if !ARCH_TEGRA_13x_SOC
select HAVE_ARM_ARCH_TIMER
select ARCH_HAS_PASR
select POWER_SUPPLY
select TEGRA_ISOMGR
select TEGRA_ISOMGR_SYSFS
select PROC_DEVICETREE
help
Support for NVIDIA Tegra 12x family of SoCs, based upon the
ARM Cortex-A15MP CPU
config TEGRA_NO_CARVEOUT
bool "Disable Tegra carveout"
default n
config ARCH_TEGRA_HAS_ARM_SCU
bool
config ARCH_TEGRA_HAS_DUAL_3D
bool
config ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
bool
config ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
bool
config ARCH_TEGRA_HAS_PCIE
bool
config ARCH_TEGRA_HAS_SATA
bool
config ARCH_TEGRA_HAS_CL_DVFS
bool
config TEGRA_AHB
bool "Enable AHB driver for NVIDIA Tegra SoCs"
default y
help
Adds AHB configuration functionality for NVIDIA Tegra SoCs,
which controls AHB bus master arbitration and some
performance parameters(priority, prefech size).
comment "Tegra board type"
config MACH_BONAIRE
bool "Bonaire board"
depends on ARCH_TEGRA_12x_SOC
select TEGRA_FPGA_PLATFORM
help
Support for NVIDIA Bonaire FPGA development platform
config MACH_ARDBEG
bool "ARDBEG board"
depends on ARCH_TEGRA_12x_SOC || ARCH_TEGRA_11x_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_MAX98090 if SND_SOC
select SYSEDP_FRAMEWORK
help
Support for NVIDIA ARDBEG Development platform
config MACH_LOKI
bool "Loki board"
depends on ARCH_TEGRA_12x_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
select LEDS_PWM
help
Support for NVIDIA LOKI Development platform
config MACH_P2360
bool "P2360 board"
depends on ARCH_TEGRA_12x_SOC
help
Support for NVIDIA P2360 Automotive Development platform
config MACH_VCM30_T124
bool "VCM30_T124(Automotive) board"
depends on ARCH_TEGRA_12x_SOC
help
Support for NVIDIA VCM30_T124 Automotive Development platform
config MACH_LAGUNA
bool "LAGUNA board"
depends on ARCH_TEGRA_12x_SOC || ARCH_TEGRA_11x_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5639 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_RT5645 if SND_SOC
select MACH_HAS_SND_SOC_TEGRA_MAX98090 if SND_SOC
help
Support for NVIDIA LAGUNA Development platform
choice
prompt "Tegra platform type"
default TEGRA_SILICON_PLATFORM
config TEGRA_SILICON_PLATFORM
bool "Silicon"
help
This enables support for a Tegra silicon platform.
config TEGRA_SIMULATION_PLATFORM
bool "Simulation"
select TEGRA_PRE_SILICON_SUPPORT
select LESS_GCC_OPT if DEBUG_KERNEL
select READABLE_ASM if DEBUG_KERNEL
select TEGRA_SIMULATION_SPLIT_MEM
help
This enables support for a Tegra simulation platform.
Select this only if you are an NVIDIA developer working
on a simulation platform.
config TEGRA_FPGA_PLATFORM
bool "FPGA"
select TEGRA_PRE_SILICON_SUPPORT
select LESS_GCC_OPT if DEBUG_KERNEL
select READABLE_ASM if DEBUG_KERNEL
help
This enables support for a Tegra FPGA platform.
Select this only if you are an NVIDIA developer working
on a FPGA platform.
endchoice
config TEGRA_PRE_SILICON_SUPPORT
bool "Enable pre-silicon platform support"
help
This enables support for Tegra early development platforms.
Select this only if you are an NVIDIA developer working on
FPGA, Emulation or Simulation.
config TEGRA_SIMULATION_SPLIT_MEM
bool "Tegra Simulation Split Memory Configuration"
default n
help
This enables support for a Tegra split memory
simulation. It can be used as part of ASIM/QT test
setup. Select this only if you are an NVIDIA developer
working on a simulation platform.
config FIQ_DEBUGGER
bool "FIQ Mode Serial Debugger"
select FIQ
select FIQ_GLUE
default n
help
The FIQ serial debugger can accept commands even when the
kernel is unresponsive due to being stuck with interrupts
disabled. Also, we can save kernel log in FIQ handler.
It will not work if FIQ not work or hardware hang.
config FIQ_DEBUGGER_NO_SLEEP
bool "Keep serial debugger active"
depends on FIQ_DEBUGGER
default n
help
Enables the serial debugger at boot. Passing
fiq_debugger.no_sleep on the kernel commandline will
override this config option.
Enable this config then serial debugger will never off.
config FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON
bool "Don't disable wakeup IRQ when debugger is active"
depends on FIQ_DEBUGGER
default n
help
Don't disable the wakeup irq when enabling the uart clock. This will
cause extra interrupts, but it makes the serial debugger usable with
on some MSM radio builds that ignore the uart clock request in power
collapse.
config FIQ_DEBUGGER_CONSOLE
bool "Console on FIQ Serial Debugger port"
depends on FIQ_DEBUGGER
default n
help
Enables a console so that printk messages are displayed on
the debugger serial port as the occur.
config FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE
bool "Put the FIQ debugger into console mode by default"
depends on FIQ_DEBUGGER_CONSOLE
default n
help
If enabled, this puts the fiq debugger into console mode by default.
Otherwise, the fiq debugger will start out in debug mode.
config TEGRA_FIQ_DEBUGGER
bool "Enable the FIQ serial debugger on Tegra"
default n
select FIQ_DEBUGGER
help
Enables the FIQ serial debugger on Tegra
config TEGRA_WDT_FIQ_SOFT_HANG_STACK_DUMP
bool "Enable Tegra system soft hang stack dump"
default n
help
This option will generate stack dump for all online CPUs upon
soft hang detection by using the FIQ debugger mechanism even
the IRQ is disabled on the CPU. This option is useful if we
only have one watchdog generating FIQ for all CPUs.
config TEGRA_PTM
bool "Enable PTM debugger on Tegra"
default n
help
This option enables PTM debugger on Tegra. This driver is used
for tracking each branch instructions executed by processor. It
can save such tracking information to the ETB buffer, which can
be further parsed by a user space program to re-construct the
complete program flows.
config TEGRA_EMC_SCALING_ENABLE
bool "Enable scaling the memory frequency"
default n
config TEGRA_CPU_DVFS
bool "Enable voltage scaling on Tegra CPU"
default y
config TEGRA_CORE_DVFS
bool "Enable voltage scaling on Tegra core"
depends on TEGRA_CPU_DVFS
default y
config TEGRA_GPU_DVFS
bool "Enable voltage scaling on Tegra GPU"
depends on TEGRA_SILICON_PLATFORM
depends on ARCH_TEGRA_12x_SOC
default y
config TEGRA_DVFS_RAIL_CONNECT_ALL
bool "Enable voltage scaling only if all rails matched by dvfs (cpu, gpu, core) are connected"
default y
help
This option adds an extra check to enable voltage scaling. Set to y
if you want to enable voltage scaling only when all the rails matched
by dvfs connect successfully to the system
config TEGRA_AVP_KERNEL_ON_MMU
bool "Use AVP MMU to relocate AVP kernel"
depends on ARCH_TEGRA_2x_SOC
default y
help
Use AVP MMU to relocate AVP kernel (nvrm_avp.bin).
config TEGRA_AVP_KERNEL_ON_SMMU
bool "Use SMMU to relocate AVP kernel"
depends on TEGRA_IOMMU_SMMU
default y
help
Use SMMU to relocate AVP kernel (nvrm_avp.bin).
config TEGRA_ARB_SEMAPHORE
bool
config TEGRA_THERMAL_THROTTLE
bool "Enable throttling of CPU speed on overtemp"
depends on CPU_FREQ
depends on THERMAL
default y
help
Also requires enabling a temperature sensor such as NCT1008.
config TEGRA_THERMAL_THROTTLE_EXACT_FREQ
bool "Use exact cpu frequency capping when thermal throttling"
depends on TEGRA_THERMAL_THROTTLE
default y if TEGRA_THERMAL_THROTTLE
default n
help
When this option is enabled, the cpu will run at the exact
frequency specified in the thermal throttle table when thermal
throttling; when disabled, the cpu frequency will clip to
the next lower frequency from the cpu frequency table.
config TEGRA_CLOCK_DEBUG_WRITE
bool "Enable debugfs write access to clock tree"
depends on DEBUG_FS
default n
config TEGRA_CLOCK_DEBUG_FUNC
bool "Enable extra debug functions to access to clock tree"
depends on TEGRA_CLOCK_DEBUG_WRITE
default n
config TEGRA_CLUSTER_CONTROL
bool
depends on ARCH_TEGRA_HAS_DUAL_CPU_CLUSTERS
default y if PM_SLEEP
config TEGRA_CPUQUIET
bool
config TEGRA_AUTO_HOTPLUG
bool "Enable automatic CPU hot-plugging"
depends on HOTPLUG_CPU && CPU_FREQ && !ARCH_CPU_PROBE_RELEASE && !ARCH_TEGRA_2x_SOC
select TEGRA_CPUQUIET
default y
help
This option enables turning CPUs off/on and switching tegra
high/low power CPU clusters automatically, corresponding to
CPU frequency scaling.
config TEGRA_MC_EARLY_ACK
bool "Enable early acknowledgement from mermory controller"
depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
default y
help
This option enables early acknowledgement from memory
controller. This feature is used to improve CPU memory
write performance.
config TEGRA_ERRATA_1252872
bool "DLL experiences internal sychronization issue"
depends on ARCH_TEGRA_14x_SOC
help
The digital DLL in the T148 A01 chip has an internal synchronization
issue that can lead to reading invalid results. These invalid results
are returned when multiple bits change in one calibration value to
the next. To work around this a two step process is used: (1) the DLL
is enabled and locked (but not sampled); and (2) the DLL clock is
disabled and the internal state machine is reinvoked (and then
sampled). This requires that the DLL is never placed in a continuous
running mode.
config TEGRA_ERRATA_1213083
bool "HOTRESET_STAT can return invalid status"
depends on ARCH_TEGRA_14x_SOC
help
On T14x it is possible to read the HOTRESET_STAT register before
the HW has had a chance to transition into the flush state. Thus
the flush status appears to be done. This errata adds a small delay
(at least 25 mcclk cycles) before polling the HOTRESET_STAT register.
config TEGRA_ERRATA_1157520
bool "Memory writes are not consistent/ordered from CPU"
depends on ARCH_TEGRA_11x_SOC
help
On T11x With early ack scoreboard on, the read/writes to
SO and Non-Cached meory are randomly not observed in the
order they are performed. Enabling this errata disables
early ack scoreboard for T11x.
config TEGRA_ERRATA_977223
bool "PTSA ring 1 to ring 0 does not account for forced coalescing"
depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC
help
The forced coalescing logic will "drop" the first request of the
coalesced pair after the ring 1 snap arbiter. This means that for
forced coalescing clients, ring 0 only sees half the requests.
Therefore the grant decrement for the ptsa would only happen 1/2 of
the expected times resulting in ring 1 input always being
high priority. A SW work around is to program the ring 1 input to
ring 0 ptsa rate to be 1/2 of the value intended.
config TEGRA_EDP_LIMITS
bool "Enforce electrical design limits on CPU rail"
depends on CPU_FREQ
depends on THERMAL
default y if ARCH_TEGRA_3x_SOC
default n
help
Limit maximum CPU frequency based on temperature and number
of on-line CPUs to keep CPU rail current within power supply
capabilities.
config TEGRA_CPU_EDP_FIXED_LIMITS
bool "Enforce fixed EDP limits on CPU rail per chip SKU"
depends on ARCH_TEGRA_11x_SOC
depends on TEGRA_EDP_LIMITS
default n
help
Enforce CPU EDP frequency limits which are fixed for a given
chip SKU. By default, the max frequency is determined optimally
for each individual chip.
config TEGRA_GPU_EDP
bool "enable GPU EDP "
depends on THERMAL
depends on TEGRA_EDP_LIMITS
depends on ARCH_TEGRA_12x_SOC
default n
help
Limit maximum GPU frequency based on temperature
to keep GPU rail current within power supply
capabilities.
config TEGRA_CPU_VOLT_CAP
bool "Allow cpu voltage to be capped based on usage metrics."
depends on TEGRA_EDP_LIMITS
default n
help
Provide userspace with an interface to dynamically adjust
CPU cap. Userspace must respect
datasheet-imposed limits.
config TEGRA_CORE_CAP
bool "Control core capping limits"
default y
help
Provide userspace control of floor and caps via sysfs and QoS
interface.
config TEGRA_EMC_TO_DDR_CLOCK
int "EMC to DDR clocks ratio"
default "2" if ARCH_TEGRA_2x_SOC
default "1"
config TEGRA_GADGET_BOOST_CPU_FREQ
int "Boost cpu frequency for tegra usb gadget"
range 0 1300 if ARCH_TEGRA_3x_SOC
range 0 1800 if ARCH_TEGRA_11x_SOC
range 0 2000 if ARCH_TEGRA_14x_SOC
range 0 2000 if ARCH_TEGRA_12x_SOC
default 0
help
Devices need to boost frequency of CPU when they are connected
to host pc through usb cable for better performance. This value
is the amount of the frequency (in Mhz) to be boosted. If it is
zero boosting frequency will not be enabled. This value will be
used only by usb gadget driver.
config TEGRA_EHCI_BOOST_CPU_FREQ
int "Boost cpu frequency(in Mhz) for tegra usb host"
range 0 1300 if ARCH_TEGRA_3x_SOC
range 0 1800 if ARCH_TEGRA_11x_SOC
range 0 2000 if ARCH_TEGRA_14x_SOC
range 0 2000 if ARCH_TEGRA_12x_SOC
default 0
help
This value is the amount of the cpu frequency (in Mhz)
to be boosted. If it is zero boosting frequency will not
be enabled. This value will be used only by usb ehci driver.
config TEGRA_CPU_FREQ_GOVERNOR_KERNEL_START
bool "Initialize CPU governor to a performance after DVFS initialization"
default 0
help
During a boot up, once DVFS is initialized, there is a period of
time in which the frequency could adjusted higher before the userspace
configures the governor by using a more performance governor for
a faster boot up. Selecting this option will make the system to choose
a performance governor once the DVFS initialization is complete. Userspace
or init script can override the governor chosen here.
config TEGRA_DYNAMIC_PWRDET
bool "Enable dynamic activation of IO level auto-detection"
default n
help
This option allows turning off tegra IO level auto-detection
when IO power is stable. If set auto-detection cells are active
only during power transitions, otherwise, the cells are active
always
config TEGRA_EDP_EXACT_FREQ
bool "Use maximum possible cpu frequency when EDP capping"
depends on TEGRA_EDP_LIMITS
default y
help
When enabled the cpu will run at the exact frequency
specified in the EDP table when EDP capping is applied; when
disabled the next lower cpufreq frequency will be used.
config TEGRA_WAKEUP_MONITOR
bool "Enable tegra wakeup monitor"
depends on PM_SLEEP
help
This option enables support for the monitor of tegra wakeups, it will
send out wakeup source and uevents which indicate suspend_prepare and
post_suspend.
config TEGRA_INTERNAL_USB_CABLE_WAKE_SUPPORT
bool "Enable Tegra internal USB cable wake support"
depends on PM_SLEEP
default n
help
Enables Tegra suspend wakeup with USB cable through Tegra
integrated hardware. Enabled for selected Tegra chipsets.
This feature allows wakeup from suspend using either
device or host type USB cable.
config TEGRA_BB_XMM_POWER
bool "Enable power driver for XMM modem"
default n
help
Enables power driver which controls gpio signals to XMM modem.
config TEGRA_BB_XMM_POWER2
tristate "Enable power driver for XMM modem (flashless)"
default n
help
Enables power driver which controls gpio signals to XMM modem
(in flashless configuration). User-mode application must
insert this LKM to initiate 2nd USB enumeration power sequence
- after modem software has been downloaded to flashless device.
config TEGRA_BBC_PROXY
bool "Enable BBC Proxy driver"
default n
help
Enables driver which handles miscellaneous services required
by the BB core. Handles initialization of EDP, ISO Bandwidth,
and Latency Allowance settings. Additional setting adjustments
can be done from user space through sysfs.
config TEGRA_BBC_THERMAL
bool "Enable BBC Thermal reporting support"
depends on NVSHM
depends on TEGRA_BBC_PROXY
default y
help
Enables the reporting of BBC-managed temperature sensors values as
thermal zones. This uses the statistics framework where the data
reside, and thus depends on the NVSHM driver to provides the API to
browse the BBC statistics and be notified of modem [re-]boot.
config TEGRA_PLLM_RESTRICTED
bool "Restrict PLLM usage as module clock source"
depends on !ARCH_TEGRA_2x_SOC
default n
help
When enabled, PLLM usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is used as a clock source with no restrictions (which
may effectively increase lower limit for core voltage).
config TEGRA_WDT_RECOVERY
bool "Enable suspend/resume watchdog recovery mechanism"
default n
help
Enables watchdog recovery mechanism to protect against
suspend/resume hangs.
config TEGRA_LP2_CPU_TIMER
bool
config TEGRA_RAIL_OFF_MULTIPLE_CPUS
bool
config TEGRA_SLOW_CSITE
bool "lower csite clock to 1 Mhz to reduce its power consumption"
default n
help
When enabled, csite will be running at 1 Mhz and the performance of
jtag, lauterbach and other debugger will be extremely slow.
config TEGRA_PREINIT_CLOCKS
bool "Preinitialize Tegra clocks to known states"
default n
help
Preinitialize Tegra clocks to known states before actual full-
scale clock initialization starts.
config TEGRA_PREPOWER_WIFI
bool "Pre-power up WiFi "
default n
help
Pre-power up the on board WiFi chip
config TEGRA_DYNAMIC_CBUS
bool "Adjust dynamically graphics clocks cumulative dvfs table"
config TEGRA_DUAL_CBUS
bool "Use two plls (PLLC2/PLLC3) as graphics clocks sources"
config TEGRA_MIGRATE_CBUS_USERS
bool "Move cbus users between source plls to optimize cumulative dvfs"
depends on TEGRA_DYNAMIC_CBUS && TEGRA_DUAL_CBUS
config TEGRA_SKIN_THROTTLE
bool "Skin Temperature throttling"
depends on TEGRA_THERMAL_THROTTLE
depends on THERM_EST
default n
help
Enable throttling to control the temperature of the skin/case
of the device.
config ARCH_TEGRA_4GB_MEMORY
bool "Full 4GB physical memory support"
default n
help
Harmless to select this even if hardware does not support full
4GB physical memory.
config TEGRA_LP1_LOW_COREVOLTAGE
bool "LP1 low core voltage"
default n
depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_11x_SOC
help
Enable support for LP1 Core voltage to set to lowest
config TEGRA_DISABLE_BBC_LATENCY_ALLOWANCE
bool "Disable BBCRW latency allowance"
help
Disables BBCRW latency allowance configuration by
clients. The BBCRW latency allowance would remain
same as boot time configured value.
config TEGRA_BASEBAND
bool "Enable integrated tegra baseband support"
default n
help
This option enables support for integrated icera baseband
This driver is used to setup shared memory space, provide
functions to handle IPC mechanism and a sysfs interface for IPC
notification which support polling on sysfs file.
config TEGRA_BASEBAND_SIMU
bool "Enable integrated tegra baseband simulation"
select TEGRA_BASEBAND
help
This option enables tegra baseband simulation when actual hardware
is not present. IPC is simulated when writing to status file which
allow high level tests in local loopback
config TEGRA_MC_PTSA
bool "Enable MC PTSA programming"
help
Enables Priority Tier Snap Arbiter programming in
Memory Controller. PTSA is a Memory Controller feature that
allows specifying the bandwidth necessary for ISO clients.
config TEGRA_ISOMGR
bool "Isochronous Bandwidth Manager "
help
When enabled, drivers for ISO units can obtain ISO BW.
The memory controller (MC) for each Tegra platform can supply
a limited amount of isochronous (real-time) bandwidth. When
enabled, isomgr will manage a pool of ISO BW.
config TEGRA_ISOMGR_POOL_KB_PER_SEC
int "Size of isomgr pool "
default 0
help
Set this maximum ISO BW (in Kbytes/sec) that platform supports.
The memory controller (MC) for each Tegra platform can supply
a limited amount of isochronous (real-time) bandwidth. Each
platform must specify the maximum amount of ISO BW that isomgr
should manage.
config TEGRA_ISOMGR_SYSFS
bool "Visibility into Isochronous Bandwidth Manager state "
depends on TEGRA_ISOMGR
help
When enabled, sysfs can be used to query isomgr state.
This is used for visibility into isomgr state. It could
be useful in debug or in understanding performance on a
running system.
config TEGRA_ISOMGR_MAX_ISO_BW_QUIRK
bool "Relax Max ISO Bw limit"
depends on TEGRA_ISOMGR
default y
help
When enabled, allows system with less ISO bw continue to
work. This is necessary for systems running at lower
EMC clock freq or on FPGA.
config TEGRA_IO_DPD
bool "Allow IO DPD"
depends on ARCH_TEGRA_3x_SOC
depends on PM_SLEEP
default y
help
Allow devices listed in tegra_list_io_dpd[] to go into
Deep Power Down (DPD) state. This is a temporary config
option until a proper way is implemented to resolve this issue.
config TEGRA_USE_DFLL_RANGE
int "Default CPU DFLL operating range"
depends on ARCH_TEGRA_HAS_CL_DVFS
range 0 3
default "0" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_21x_SOC
default "1" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_13x_SOC
default "2" if TEGRA_SILICON_PLATFORM && ARCH_TEGRA_11x_SOC
default "1"
help
Defines default range for dynamic frequency lock loop (DFLL)
to be used as CPU clock source:
"0" - DFLL is not used,
"1" - DFLL is used as a source for all CPU rates
"2" - DFLL is used only for high rates above crossover with
PLL dvfs curve
"3" - DFLL usage is controlled by thermal cooling device
config REGULATOR_TEGRA_DFLL_BYPASS
bool "Use dfll bypass regulator"
depends on ARCH_TEGRA_HAS_CL_DVFS
default n
help
Enables use of dfll bypass interfaces for voltage control
by s/w driver.
config TEGRA_TIMER_HZ
int "Kernel HZ (jiffies per second)"
default "100" if TEGRA_PRE_SILICON_SUPPORT
default "1000"
config TEGRA_SOCTHERM
bool "Enable soctherm"
depends on ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC || ARCH_TEGRA_12x_SOC
default y
help
Enables use of soctherm for thermal management.
config TEGRA_USE_SECURE_KERNEL
bool "Boot the linux kernel in non-secure mode"
help
When enabled, the CPU will boot in the non-secure mode and issue
SMCs in order to access secure registers. SMC requests would be
serviced by a third party software component running in the secure
mode.
config TEGRA_VIRTUAL_CPUID
bool "virtualized CPUID"
depends on !TEGRA_USE_SECURE_KERNEL
depends on ARCH_TEGRA_HAS_SYMMETRIC_CPU_PWR_GATE
default n
help
Enables virtualized CPUID.
config TEGRA_NVDUMPER
bool "Enable NvDumper for post-mortem debugging"
default n
help
The nvdumper is a tool that saves a copy of RAM following a crash.
nvdumper kernel module tracks whether the system has been rebooted
cleanly. It does this by writing 'dirty' to a fixed physical memory
address when the kernel starts.
Then, on a planned reboot, we write 'clean' to this location.
The bootloader can then examine this location and see if the reboot
was dirty or clean.
It will dump the contents of memory after a dirty reboot.
This tool would be helpful for debugging kernel crash.
In order to use this feature, you should enable debug feature in
bootloader compiling option also (-DENABLE_NVDUMPER).
You can dump RAM with nvflash tool in dirty boot status.
usage: nvflash --dumpram [phy. RAM offset] [length]
config TEGRA_ARBITRATION_EMEM_INTR
bool "Enable the ARBITRATION_EMEM interrupt in the MC"
help
Enable this to allow the kernel to track arbitration conflicts
in the memory controller.
config TEGRA_CORE_EDP_LIMITS
bool "Enforce electrical design limits on core rail"
depends on TEGRA_SILICON_PLATFORM
depends on THERMAL
default n
help
Limit maximum GPU and memory frequency to keep core rail current
within power supply capabilities.
config TEGRA_PLLM_SCALED
bool "Enable memory PLLM run time scaling"
depends on TEGRA_DUAL_CBUS
select TEGRA_PLLM_RESTRICTED
default n
help
When enabled, memory PLLM can be scaled at run time to reduce
granularity of possible memory rate steps. In this case PLLC
provides a backup memory clock while PLLM is re-locking to the
new rate.
config ARCH_TEGRA_VIC
bool "Tegra Video Image Compositor present"
default y
help
Say Y here if the SOC supports the Tegra Video Image Compositor.
Note that this not the same as the ARM Vectored Interrupt Controller.
config TEGRA_USE_NCT
bool "Enable NCT partition access"
help
When enabled, we can read non-volatile items from NCT partition.
config TEGRA_VDD_CORE_OVERRIDE
bool "Enable core rail override support"
depends on TEGRA_SILICON_PLATFORM
default n
select CONFIG_TEGRA_CORE_CAP
help
When enabled, core rail can be fixed and locked at specified voltage
within override range, and core modules clocks are capped at rates
safe at override level.
config TEGRA_GMI
bool
config TEGRA_SOC_TIMERS
bool "Enable support for SOC timers"
default n
help
When enabled, cpu clock events will be using SOC timers instead
of arm private timers.
config TEGRA_LP0_IN_IDLE
bool "Enable support LP0-in-idle state"
default n
config TEGRA_HDMI_PRIMARY
bool "Use HDMI as primary display"
depends on TEGRA_DC
depends on !FRAMEBUFFER_CONSOLE
help
Configure system to support HDMI as the primary display.
When enabled, dispA/fb0 will be configured to use HDMI.
config TEGRA_USE_SIMON
bool "Use Tegra Silicon Monitor"
default n
help
Enable Tegra silicon state monitoring, grading, and notification.
config AID_FUSE
bool "Support AID fuse reads"
default n if ARCH_TEGRA_11x_SOC || ARCH_TEGRA_14x_SOC || \
(ARCH_TEGRA_12x_SOC && !ARCH_TEGRA_13x_SOC)
default y
help
When enabled, allows sysfs reads of the AID fuse, which contains
the chip family ID and a chip-unique Tegra ID. Supported on t132+.
endif