/* * Copyright (C) 2011 NVIDIA, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA * 02111-1307, USA */ #include #include #include "board-enterprise.h" #include "tegra3_emc.h" static const struct tegra_emc_table tegra_enterprise_emc_tables_h5tc2g[] = { { 0x30, /* Rev 3.0 */ 27000, /* SDRAM frquency */ { 0x00000001, /* EMC_RC */ 0x00000004, /* EMC_RFC */ 0x00000000, /* EMC_RAS */ 0x00000000, /* EMC_RP */ 0x00000002, /* EMC_R2W */ 0x0000000A, /* EMC_W2R */ 0x00000003, /* EMC_R2P */ 0x0000000B, /* EMC_W2P */ 0x00000000, /* EMC_RD_RCD */ 0x00000000, /* EMC_WR_RCD */ 0x00000003, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ 0x00000003, /* EMC_QUSE */ 0x00000004, /* EMC_QRST */ 0x00000007, /* EMC_QSAFE */ 0x0000000B, /* EMC_RDV */ 0x000000CB, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000032, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002, /* EMC_PDEX2WR */ 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x00000007, /* EMC_AR2PDEN */ 0x0000000F, /* EMC_RW2PDEN */ 0x00000005, /* EMC_TXSR */ 0x00000005, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000001, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ 0x000000D3, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00008088, /* EMC_FBIO_CFG5 */ 0x00780004, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00000010, /* EMC_DLL_XFORM_DQS0 */ 0x00000010, /* EMC_DLL_XFORM_DQS1 */ 0x00000010, /* EMC_DLL_XFORM_DQS2 */ 0x00000010, /* EMC_DLL_XFORM_DQS3 */ 0x00000010, /* EMC_DLL_XFORM_DQS4 */ 0x00000010, /* EMC_DLL_XFORM_DQS5 */ 0x00000010, /* EMC_DLL_XFORM_DQS6 */ 0x00000010, /* EMC_DLL_XFORM_DQS7 */ 0x00000018, /* EMC_DLL_XFORM_QUSE0 */ 0x00000018, /* EMC_DLL_XFORM_QUSE1 */ 0x00000018, /* EMC_DLL_XFORM_QUSE2 */ 0x00000018, /* EMC_DLL_XFORM_QUSE3 */ 0x00000018, /* EMC_DLL_XFORM_QUSE4 */ 0x00000018, /* EMC_DLL_XFORM_QUSE5 */ 0x00000018, /* EMC_DLL_XFORM_QUSE6 */ 0x00000018, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ 0x000002A0, /* EMC_XM2CMDPADCTRL */ 0x0800211D, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77FFC084, /* EMC_XM2CLKPADCTRL */ 0x01F1F108, /* EMC_XM2COMPPADCTRL */ 0x07075504, /* EMC_XM2VTTGENPADCTRL */ 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ 0x0800012D, /* EMC_XM2QUSEPADCTRL */ 0x08000000, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00000000, /* EMC_ZCAL_INTERVAL */ 0x00000040, /* EMC_ZCAL_WAIT_CNT */ 0x000C000C, /* EMC_MRS_WAIT_CNT */ 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000029E, /* EMC_DYN_SELF_REF_CONTROL */ 0x00010001, /* MC_EMEM_ARB_CFG */ 0x8000000A, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x0000000F, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ 0x0000000F, /* MC_EMEM_ARB_TIMING_W2R */ 0x0F070506, /* MC_EMEM_ARB_DA_TURNS */ 0x00140905, /* MC_EMEM_ARB_DA_COVERS */ 0x78430306, /* MC_EMEM_ARB_MISC0 */ 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ 0x00001221, /* DDR3 Mode Register 0 */ 0x00100003, /* DDR3 Mode Register 1 */ 0x00200008, /* DDR3 Mode Register 2 */ }, { 0x30, /* Rev 3.0 */ 54000, /* SDRAM frquency */ { 0x00000002, /* EMC_RC */ 0x00000008, /* EMC_RFC */ 0x00000001, /* EMC_RAS */ 0x00000000, /* EMC_RP */ 0x00000002, /* EMC_R2W */ 0x0000000A, /* EMC_W2R */ 0x00000003, /* EMC_R2P */ 0x0000000B, /* EMC_W2P */ 0x00000000, /* EMC_RD_RCD */ 0x00000000, /* EMC_WR_RCD */ 0x00000003, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ 0x00000003, /* EMC_QUSE */ 0x00000004, /* EMC_QRST */ 0x00000007, /* EMC_QSAFE */ 0x0000000B, /* EMC_RDV */ 0x00000198, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000066, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002, /* EMC_PDEX2WR */ 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x00000007, /* EMC_AR2PDEN */ 0x0000000F, /* EMC_RW2PDEN */ 0x0000000A, /* EMC_TXSR */ 0x0000000A, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000002, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ 0x000001A6, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00008088, /* EMC_FBIO_CFG5 */ 0x00780004, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00000010, /* EMC_DLL_XFORM_DQS0 */ 0x00000010, /* EMC_DLL_XFORM_DQS1 */ 0x00000010, /* EMC_DLL_XFORM_DQS2 */ 0x00000010, /* EMC_DLL_XFORM_DQS3 */ 0x00000010, /* EMC_DLL_XFORM_DQS4 */ 0x00000010, /* EMC_DLL_XFORM_DQS5 */ 0x00000010, /* EMC_DLL_XFORM_DQS6 */ 0x00000010, /* EMC_DLL_XFORM_DQS7 */ 0x00000018, /* EMC_DLL_XFORM_QUSE0 */ 0x00000018, /* EMC_DLL_XFORM_QUSE1 */ 0x00000018, /* EMC_DLL_XFORM_QUSE2 */ 0x00000018, /* EMC_DLL_XFORM_QUSE3 */ 0x00000018, /* EMC_DLL_XFORM_QUSE4 */ 0x00000018, /* EMC_DLL_XFORM_QUSE5 */ 0x00000018, /* EMC_DLL_XFORM_QUSE6 */ 0x00000018, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ 0x000002A0, /* EMC_XM2CMDPADCTRL */ 0x0800211D, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77FFC084, /* EMC_XM2CLKPADCTRL */ 0x01F1F108, /* EMC_XM2COMPPADCTRL */ 0x07075504, /* EMC_XM2VTTGENPADCTRL */ 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ 0x0800012D, /* EMC_XM2QUSEPADCTRL */ 0x08000000, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00000000, /* EMC_ZCAL_INTERVAL */ 0x00000040, /* EMC_ZCAL_WAIT_CNT */ 0x000C000C, /* EMC_MRS_WAIT_CNT */ 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x80000439, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000001, /* MC_EMEM_ARB_CFG */ 0x80000014, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ 0x00000001, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x0000000F, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ 0x0000000F, /* MC_EMEM_ARB_TIMING_W2R */ 0x0F070506, /* MC_EMEM_ARB_DA_TURNS */ 0x00140905, /* MC_EMEM_ARB_DA_COVERS */ 0x78430506, /* MC_EMEM_ARB_MISC0 */ 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ 0x00001221, /* DDR3 Mode Register 0 */ 0x00100003, /* DDR3 Mode Register 1 */ 0x00200008, /* DDR3 Mode Register 2 */ }, { 0x30, /* Rev 3.0 */ 108000, /* SDRAM frquency */ { 0x00000005, /* EMC_RC */ 0x00000011, /* EMC_RFC */ 0x00000003, /* EMC_RAS */ 0x00000001, /* EMC_RP */ 0x00000002, /* EMC_R2W */ 0x0000000A, /* EMC_W2R */ 0x00000003, /* EMC_R2P */ 0x0000000B, /* EMC_W2P */ 0x00000001, /* EMC_RD_RCD */ 0x00000001, /* EMC_WR_RCD */ 0x00000003, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ 0x00000003, /* EMC_QUSE */ 0x00000004, /* EMC_QRST */ 0x00000007, /* EMC_QSAFE */ 0x0000000B, /* EMC_RDV */ 0x00000330, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x000000CC, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002, /* EMC_PDEX2WR */ 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x00000007, /* EMC_AR2PDEN */ 0x0000000F, /* EMC_RW2PDEN */ 0x00000013, /* EMC_TXSR */ 0x00000013, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000004, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ 0x0000034B, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00008088, /* EMC_FBIO_CFG5 */ 0x00780004, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00000010, /* EMC_DLL_XFORM_DQS0 */ 0x00000010, /* EMC_DLL_XFORM_DQS1 */ 0x00000010, /* EMC_DLL_XFORM_DQS2 */ 0x00000010, /* EMC_DLL_XFORM_DQS3 */ 0x00000010, /* EMC_DLL_XFORM_DQS4 */ 0x00000010, /* EMC_DLL_XFORM_DQS5 */ 0x00000010, /* EMC_DLL_XFORM_DQS6 */ 0x00000010, /* EMC_DLL_XFORM_DQS7 */ 0x00000018, /* EMC_DLL_XFORM_QUSE0 */ 0x00000018, /* EMC_DLL_XFORM_QUSE1 */ 0x00000018, /* EMC_DLL_XFORM_QUSE2 */ 0x00000018, /* EMC_DLL_XFORM_QUSE3 */ 0x00000018, /* EMC_DLL_XFORM_QUSE4 */ 0x00000018, /* EMC_DLL_XFORM_QUSE5 */ 0x00000018, /* EMC_DLL_XFORM_QUSE6 */ 0x00000018, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ 0x000002A0, /* EMC_XM2CMDPADCTRL */ 0x0800211D, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77FFC084, /* EMC_XM2CLKPADCTRL */ 0x01F1F108, /* EMC_XM2COMPPADCTRL */ 0x07075504, /* EMC_XM2VTTGENPADCTRL */ 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ 0x0800012D, /* EMC_XM2QUSEPADCTRL */ 0x08000000, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00000000, /* EMC_ZCAL_INTERVAL */ 0x00000040, /* EMC_ZCAL_WAIT_CNT */ 0x000C000C, /* EMC_MRS_WAIT_CNT */ 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x8000076E, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000003, /* MC_EMEM_ARB_CFG */ 0x80000027, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ 0x00000006, /* MC_EMEM_ARB_TIMING_RC */ 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x0000000F, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000007, /* MC_EMEM_ARB_TIMING_R2W */ 0x0000000F, /* MC_EMEM_ARB_TIMING_W2R */ 0x0F070506, /* MC_EMEM_ARB_DA_TURNS */ 0x00140906, /* MC_EMEM_ARB_DA_COVERS */ 0x78440A07, /* MC_EMEM_ARB_MISC0 */ 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ 0x00001221, /* DDR3 Mode Register 0 */ 0x00100003, /* DDR3 Mode Register 1 */ 0x00200008, /* DDR3 Mode Register 2 */ }, { 0x30, /* Rev 3.0 */ 333500, /* SDRAM frquency */ { 0x00000010, /* EMC_RC */ 0x00000035, /* EMC_RFC */ 0x0000000B, /* EMC_RAS */ 0x00000004, /* EMC_RP */ 0x00000003, /* EMC_R2W */ 0x00000009, /* EMC_W2R */ 0x00000003, /* EMC_R2P */ 0x0000000A, /* EMC_W2P */ 0x00000004, /* EMC_RD_RCD */ 0x00000004, /* EMC_WR_RCD */ 0x00000003, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000004, /* EMC_WDV */ 0x00000004, /* EMC_QUSE */ 0x00000004, /* EMC_QRST */ 0x00000008, /* EMC_QSAFE */ 0x0000000D, /* EMC_RDV */ 0x000009E9, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x0000027A, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002, /* EMC_PDEX2WR */ 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x00000007, /* EMC_AR2PDEN */ 0x0000000E, /* EMC_RW2PDEN */ 0x00000039, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x0000000A, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000004, /* EMC_TCLKSTABLE */ 0x00000005, /* EMC_TCLKSTOP */ 0x00000A2A, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00008088, /* EMC_FBIO_CFG5 */ 0x00260004, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00000010, /* EMC_DLL_XFORM_DQS0 */ 0x00000010, /* EMC_DLL_XFORM_DQS1 */ 0x00000010, /* EMC_DLL_XFORM_DQS2 */ 0x00000010, /* EMC_DLL_XFORM_DQS3 */ 0x00000010, /* EMC_DLL_XFORM_DQS4 */ 0x00000010, /* EMC_DLL_XFORM_DQS5 */ 0x00000010, /* EMC_DLL_XFORM_DQS6 */ 0x00000010, /* EMC_DLL_XFORM_DQS7 */ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x0000A010, /* EMC_DLL_XFORM_DQ0 */ 0x0000A010, /* EMC_DLL_XFORM_DQ1 */ 0x0000A010, /* EMC_DLL_XFORM_DQ2 */ 0x0000A010, /* EMC_DLL_XFORM_DQ3 */ 0x000002A0, /* EMC_XM2CMDPADCTRL */ 0x0800013D, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77FFC084, /* EMC_XM2CLKPADCTRL */ 0x01F1F508, /* EMC_XM2COMPPADCTRL */ 0x07075504, /* EMC_XM2VTTGENPADCTRL */ 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ 0x0800011D, /* EMC_XM2QUSEPADCTRL */ 0x08000021, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00000000, /* EMC_ZCAL_INTERVAL */ 0x00000040, /* EMC_ZCAL_WAIT_CNT */ 0x01CB000C, /* EMC_MRS_WAIT_CNT */ 0xE0F11111, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800014D4, /* EMC_DYN_SELF_REF_CONTROL */ 0x0000000A, /* MC_EMEM_ARB_CFG */ 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ 0x0000000A, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000009, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000003, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x0000000E, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000006, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000005, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000008, /* MC_EMEM_ARB_TIMING_R2W */ 0x0000000E, /* MC_EMEM_ARB_TIMING_W2R */ 0x0E080506, /* MC_EMEM_ARB_DA_TURNS */ 0x00170D10, /* MC_EMEM_ARB_DA_COVERS */ 0x784A1F11, /* MC_EMEM_ARB_MISC0 */ 0x001F0001, /* MC_EMEM_ARB_RING1_THROTTLE */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x00000000, /* EMC_AUTO_CAL_INTERVAL */ 0x00001321, /* DDR3 Mode Register 0 */ 0x00100002, /* DDR3 Mode Register 1 */ 0x00200000, /* DDR3 Mode Register 2 */ }, { 0x30, /* Rev 2.0 */ 533000, /* SDRAM frquency */ { 0x00000018, /* EMC_RC */ 0x00000054, /* EMC_RFC */ 0x00000011, /* EMC_RAS */ 0x00000006, /* EMC_RP */ 0x00000003, /* EMC_R2W */ 0x00000009, /* EMC_W2R */ 0x00000002, /* EMC_R2P */ 0x0000000D, /* EMC_W2P */ 0x00000006, /* EMC_RD_RCD */ 0x00000006, /* EMC_WR_RCD */ 0x00000002, /* EMC_RRD */ 0x00000001, /* EMC_REXT */ 0x00000000, /* EMC_WEXT */ 0x00000005, /* EMC_WDV */ 0x00000008, /* EMC_QUSE */ 0x00000006, /* EMC_QRST */ 0x0000000A, /* EMC_QSAFE */ 0x00000010, /* EMC_RDV */ 0x00000FFD, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x000003FF, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000002, /* EMC_PDEX2WR */ 0x00000002, /* EMC_PDEX2RD */ 0x00000001, /* EMC_PCHG2PDEN */ 0x00000000, /* EMC_ACT2PDEN */ 0x0000000A, /* EMC_AR2PDEN */ 0x00000012, /* EMC_RW2PDEN */ 0x0000005B, /* EMC_TXSR */ 0x00000200, /* EMC_TXSRDLL */ 0x00000004, /* EMC_TCKE */ 0x00000010, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000005, /* EMC_TCLKSTABLE */ 0x00000006, /* EMC_TCLKSTOP */ 0x0000103E, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000006, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00007088, /* EMC_FBIO_CFG5 */ 0xF0120441, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00010000, /* EMC_DLL_XFORM_DQS0 */ 0x00010000, /* EMC_DLL_XFORM_DQS1 */ 0x00010000, /* EMC_DLL_XFORM_DQS2 */ 0x00010000, /* EMC_DLL_XFORM_DQS3 */ 0x00010000, /* EMC_DLL_XFORM_DQS4 */ 0x00010000, /* EMC_DLL_XFORM_DQS5 */ 0x00010000, /* EMC_DLL_XFORM_DQS6 */ 0x00010000, /* EMC_DLL_XFORM_DQS7 */ 0x00008000, /* EMC_DLL_XFORM_QUSE0 */ 0x00008000, /* EMC_DLL_XFORM_QUSE1 */ 0x00008000, /* EMC_DLL_XFORM_QUSE2 */ 0x00008000, /* EMC_DLL_XFORM_QUSE3 */ 0x00008000, /* EMC_DLL_XFORM_QUSE4 */ 0x00008000, /* EMC_DLL_XFORM_QUSE5 */ 0x00008000, /* EMC_DLL_XFORM_QUSE6 */ 0x00008000, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x00020000, /* EMC_DLL_XFORM_DQ0 */ 0x00020000, /* EMC_DLL_XFORM_DQ1 */ 0x00020000, /* EMC_DLL_XFORM_DQ2 */ 0x00020000, /* EMC_DLL_XFORM_DQ3 */ 0x000202A0, /* EMC_XM2CMDPADCTRL */ 0x0800013D, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77FFD884, /* EMC_XM2CLKPADCTRL */ 0x01F1F508, /* EMC_XM2COMPPADCTRL */ 0x07077404, /* EMC_XM2VTTGENPADCTRL */ 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ 0x0800011D, /* EMC_XM2QUSEPADCTRL */ 0x08000021, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00020000, /* EMC_ZCAL_INTERVAL */ 0x00000040, /* EMC_ZCAL_WAIT_CNT */ 0x012B000C, /* EMC_MRS_WAIT_CNT */ 0xA0F10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800020AE, /* EMC_DYN_SELF_REF_CONTROL */ 0x00000008, /* MC_EMEM_ARB_CFG */ 0x80000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ 0x0000000D, /* MC_EMEM_ARB_TIMING_RC */ 0x00000008, /* MC_EMEM_ARB_TIMING_RAS */ 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ 0x0010090D, /* MC_EMEM_ARB_DA_COVERS */ 0x7028180E, /* MC_EMEM_ARB_MISC0 */ 0x001F0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x00000010, /* EMC_AUTO_CAL_INTERVAL */ 0x00001941, /* DDR3 Mode Register 0 */ 0x00100002, /* DDR3 Mode Register 1 */ 0x00200008, /* DDR3 Mode Register 2 */ }, { 0x30, /* Rev 3.0 */ 667000, /* SDRAM frquency */ { 0x00000021, /* EMC_RC */ 0x00000073, /* EMC_RFC */ 0x00000018, /* EMC_RAS */ 0x0000000A, /* EMC_RP */ 0x00000006, /* EMC_R2W */ 0x0000000E, /* EMC_W2R */ 0x00000005, /* EMC_R2P */ 0x00000013, /* EMC_W2P */ 0x0000000A, /* EMC_RD_RCD */ 0x0000000A, /* EMC_WR_RCD */ 0x00000004, /* EMC_RRD */ 0x00000003, /* EMC_REXT */ 0x00000002, /* EMC_WEXT */ 0x00000007, /* EMC_WDV */ 0x0000000A, /* EMC_QUSE */ 0x00000009, /* EMC_QRST */ 0x00000008, /* EMC_QSAFE */ 0x00000013, /* EMC_RDV */ 0x000013AE, /* EMC_REFRESH */ 0x00000000, /* EMC_BURST_REFRESH_NUM */ 0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */ 0x00000006, /* EMC_PDEX2WR */ 0x00000006, /* EMC_PDEX2RD */ 0x00000005, /* EMC_PCHG2PDEN */ 0x00000004, /* EMC_ACT2PDEN */ 0x00000010, /* EMC_AR2PDEN */ 0x0000001A, /* EMC_RW2PDEN */ 0x0000007C, /* EMC_TXSR */ 0x0000020A, /* EMC_TXSRDLL */ 0x00000009, /* EMC_TCKE */ 0x00000019, /* EMC_TFAW */ 0x00000000, /* EMC_TRPAB */ 0x00000008, /* EMC_TCLKSTABLE */ 0x00000009, /* EMC_TCLKSTOP */ 0x000014B7, /* EMC_TREFBW */ 0x00000000, /* EMC_QUSE_EXTRA */ 0x00000004, /* EMC_FBIO_CFG6 */ 0x00000000, /* EMC_ODT_WRITE */ 0x00000000, /* EMC_ODT_READ */ 0x00009088, /* EMC_FBIO_CFG5 */ 0xF00B0401, /* EMC_CFG_DIG_DLL */ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ 0x00010000, /* EMC_DLL_XFORM_DQS0 */ 0x00010000, /* EMC_DLL_XFORM_DQS1 */ 0x00010000, /* EMC_DLL_XFORM_DQS2 */ 0x00010000, /* EMC_DLL_XFORM_DQS3 */ 0x00010000, /* EMC_DLL_XFORM_DQS4 */ 0x00010000, /* EMC_DLL_XFORM_DQS5 */ 0x00010000, /* EMC_DLL_XFORM_DQS6 */ 0x00010000, /* EMC_DLL_XFORM_DQS7 */ 0x00014000, /* EMC_DLL_XFORM_QUSE0 */ 0x00014000, /* EMC_DLL_XFORM_QUSE1 */ 0x00014000, /* EMC_DLL_XFORM_QUSE2 */ 0x00014000, /* EMC_DLL_XFORM_QUSE3 */ 0x00014000, /* EMC_DLL_XFORM_QUSE4 */ 0x00014000, /* EMC_DLL_XFORM_QUSE5 */ 0x00014000, /* EMC_DLL_XFORM_QUSE6 */ 0x00014000, /* EMC_DLL_XFORM_QUSE7 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ 0x0000400C, /* EMC_DLL_XFORM_DQ0 */ 0x0000400C, /* EMC_DLL_XFORM_DQ1 */ 0x0000400C, /* EMC_DLL_XFORM_DQ2 */ 0x0000400C, /* EMC_DLL_XFORM_DQ3 */ 0x000002A0, /* EMC_XM2CMDPADCTRL */ 0x0800013D, /* EMC_XM2DQSPADCTRL2 */ 0x00000000, /* EMC_XM2DQPADCTRL2 */ 0x77FFC084, /* EMC_XM2CLKPADCTRL */ 0x01F1F508, /* EMC_XM2COMPPADCTRL */ 0x07077404, /* EMC_XM2VTTGENPADCTRL */ 0x00000007, /* EMC_XM2VTTGENPADCTRL2 */ 0x0800011D, /* EMC_XM2QUSEPADCTRL */ 0x08000021, /* EMC_XM2DQSPADCTRL3 */ 0x00000802, /* EMC_CTT_TERM_CTRL */ 0x00000000, /* EMC_ZCAL_INTERVAL */ 0x00000040, /* EMC_ZCAL_WAIT_CNT */ 0x0196000C, /* EMC_MRS_WAIT_CNT */ 0xA0F10000, /* EMC_AUTO_CAL_CONFIG */ 0x00000000, /* EMC_CTT */ 0x00000000, /* EMC_CTT_DURATION */ 0x800028A5, /* EMC_DYN_SELF_REF_CONTROL */ 0x0000000A, /* MC_EMEM_ARB_CFG */ 0x80000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ 0x00000012, /* MC_EMEM_ARB_TIMING_RC */ 0x0000000B, /* MC_EMEM_ARB_TIMING_RAS */ 0x0000000C, /* MC_EMEM_ARB_TIMING_FAW */ 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ 0x0000000C, /* MC_EMEM_ARB_TIMING_WAP2PRE */ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */ 0x00000003, /* MC_EMEM_ARB_TIMING_W2W */ 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ 0x09050303, /* MC_EMEM_ARB_DA_TURNS */ 0x00170F12, /* MC_EMEM_ARB_DA_COVERS */ 0x706A1F13, /* MC_EMEM_ARB_MISC0 */ 0x001F0000, /* MC_EMEM_ARB_RING1_THROTTLE */ }, 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ 0x00000010, /* EMC_AUTO_CAL_INTERVAL */ 0x00001b71, /* DDR3 Mode Register 0 */ 0x00100002, /* DDR3 Mode Register 1 */ 0x00200018, /* DDR3 Mode Register 2 */ } }; int tegra_enterprise_emc_init(void) { tegra_init_emc(tegra_enterprise_emc_tables_h5tc2g, ARRAY_SIZE(tegra_enterprise_emc_tables_h5tc2g)); return 0; }