/*
 * arch/arm/mach-tegra/include/mach/tegra2_i2s.h
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Iliyan Malchev <malchev@google.com>
 *
 * Copyright (C) 2010-2011 NVIDIA Corporation
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __ARCH_ARM_MACH_TEGRA2_I2S_H
#define __ARCH_ARM_MACH_TEGRA2_I2S_H

#include <linux/kernel.h>
#include <linux/types.h>
#include <mach/tegra_i2s.h>


/* Offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */

#define I2S_I2S_CTRL_0			0
#define I2S_I2S_STATUS_0		4
#define I2S_I2S_TIMING_0		8
#define I2S_I2S_FIFO_SCR_0		0x0c
#define I2S_I2S_PCM_CTRL_0		0x10
#define I2S_I2S_NW_CTRL_0		0x14
#define I2S_TDM_CTRL_0		0x20
#define I2S_TDM_TX_RX_CTRL_0	0x24
#define I2S_I2S_FIFO1_0			0x40
#define I2S_I2S_FIFO2_0			0x80

/*
 * I2S_I2S_CTRL_0
 */

#define I2S_I2S_CTRL_FIFO2_TX_ENABLE		(1<<30)
#define I2S_I2S_CTRL_FIFO1_ENABLE		(1<<29)
#define I2S_I2S_CTRL_FIFO2_ENABLE		(1<<28)
#define I2S_I2S_CTRL_FIFO1_RX_ENABLE		(1<<27)
#define I2S_I2S_CTRL_FIFO_LPBK_ENABLE		(1<<26)
#define I2S_I2S_CTRL_MASTER_ENABLE		(1<<25)
#define I2S_I2S_CTRL_L_R_CTRL			(1<<24)

#define I2S_BIT_FORMAT_I2S 0
#define I2S_BIT_FORMAT_RJM 1
#define I2S_BIT_FORMAT_LJM 2
#define I2S_BIT_FORMAT_DSP 3
#define I2S_BIT_FORMAT_SHIFT 10

#define I2S_I2S_CTRL_BIT_FORMAT_MASK		(3<<10)
#define I2S_I2S_CTRL_BIT_FORMAT_I2S		(I2S_BIT_FORMAT_I2S<<10)
#define I2S_I2S_CTRL_BIT_FORMAT_RJM		(I2S_BIT_FORMAT_RJM<<10)
#define I2S_I2S_CTRL_BIT_FORMAT_LJM		(I2S_BIT_FORMAT_LJM<<10)
#define I2S_I2S_CTRL_BIT_FORMAT_DSP		(I2S_BIT_FORMAT_DSP<<10)

#define I2S_BIT_SIZE_16 0
#define I2S_BIT_SIZE_20 1
#define I2S_BIT_SIZE_24 2
#define I2S_BIT_SIZE_32 3
#define I2S_BIT_SIZE_SHIFT 8

#define I2S_I2S_CTRL_BIT_SIZE_MASK	\
		(3 << I2S_BIT_SIZE_SHIFT)
#define I2S_I2S_CTRL_BIT_SIZE_16	\
		(I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT)
#define I2S_I2S_CTRL_BIT_SIZE_20	\
		(I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT)
#define I2S_I2S_CTRL_BIT_SIZE_24	\
		(I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT)
#define I2S_I2S_CTRL_BIT_SIZE_32	\
		(I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT)

#define I2S_FIFO_16_LSB 0
#define I2S_FIFO_20_LSB 1
#define I2S_FIFO_24_LSB 2
#define I2S_FIFO_32	 3
#define I2S_FIFO_PACKED 7
#define I2S_FIFO_SHIFT  4

#define I2S_I2S_CTRL_FIFO_FORMAT_MASK		(7<<4)
#define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB	\
			(I2S_FIFO_16_LSB << I2S_FIFO_SHIFT)
#define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB	\
			(I2S_FIFO_20_LSB << I2S_FIFO_SHIFT)
#define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB	\
			(I2S_FIFO_24_LSB << I2S_FIFO_SHIFT)
#define I2S_I2S_CTRL_FIFO_FORMAT_32	\
			(I2S_FIFO_32 << I2S_FIFO_SHIFT)
#define I2S_I2S_CTRL_FIFO_FORMAT_PACKED	\
			(I2S_FIFO_PACKED << I2S_FIFO_SHIFT)

// Left/Right Control Polarity. 0= Left channel when LRCK is low,
// Right channel  when LRCK is high, 1= vice versa
#define I2S_LRCK_LEFT_LOW	0
#define I2S_LRCK_RIGHT_LOW	1
#define I2S_LRCK_SHIFT		24


#define I2S_I2S_CTRL_LRCK_MASK		(1<<I2S_LRCK_SHIFT)
#define I2S_I2S_CTRL_LRCK_L_LOW		(I2S_LRCK_LEFT_LOW << I2S_LRCK_SHIFT)
#define I2S_I2S_CTRL_LRCK_R_LOW		(I2S_LRCK_RIGHT_LOW << I2S_LRCK_SHIFT)


#define I2S_I2S_IE_FIFO1_ERR			(1<<3)
#define I2S_I2S_IE_FIFO2_ERR			(1<<2)
#define I2S_I2S_QE_FIFO1			(1<<1)
#define I2S_I2S_QE_FIFO2			(1<<0)

/*
 * I2S_I2S_STATUS_0
 */

#define I2S_I2S_STATUS_FIFO1_RDY		(1<<31)
#define I2S_I2S_STATUS_FIFO2_RDY		(1<<30)
#define I2S_I2S_STATUS_FIFO1_BSY		(1<<29)
#define I2S_I2S_STATUS_FIFO2_BSY		(1<<28)
#define I2S_I2S_STATUS_FIFO1_ERR		(1<<3)
#define I2S_I2S_STATUS_FIFO2_ERR		(1<<2)
#define I2S_I2S_STATUS_QS_FIFO1			(1<<1)
#define I2S_I2S_STATUS_QS_FIFO2			(1<<0)

#define I2S_I2S_FIFO_TX_BUSY	I2S_I2S_STATUS_FIFO1_BSY
#define I2S_I2S_FIFO_TX_QS	I2S_I2S_STATUS_QS_FIFO1
#define I2S_I2S_FIFO_RX_BUSY	I2S_I2S_STATUS_FIFO2_BSY
#define I2S_I2S_FIFO_RX_QS	I2S_I2S_STATUS_QS_FIFO2

/*
 * I2S_I2S_TIMING_0
 */

#define I2S_I2S_TIMING_NON_SYM_ENABLE		(1<<12)
#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT_MASK	0x7ff
#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT	(1<<0)

/*
 * I2S_I2S_FIFO_SCR_0
 */

#define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK	0x3f
#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT	24
#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT	16

#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_MASK	(0x3f<<24)
#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_MASK	(0x3f<<16)

#define I2S_I2S_FIFO_SCR_FIFO2_CLR		(1<<12)
#define I2S_I2S_FIFO_SCR_FIFO1_CLR		(1<<8)

#define I2S_FIFO_ATN_LVL_ONE_SLOT	0
#define I2S_FIFO_ATN_LVL_FOUR_SLOTS	1
#define I2S_FIFO_ATN_LVL_EIGHT_SLOTS	2
#define I2S_FIFO_ATN_LVL_TWELVE_SLOTS	3
#define I2S_FIFO2_ATN_LVL_SHIFT		4
#define I2S_FIFO1_ATN_LVL_SHIFT		0

#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK	\
		(3 << I2S_FIFO2_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT	\
		(I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO2_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS	\
		(I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS	\
		(I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS	\
		(I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)

#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK	\
		(3 << I2S_FIFO1_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT	\
		(I2S_FIFO_ATN_LVL_ONE_SLOT << I2S_FIFO1_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS	\
		(I2S_FIFO_ATN_LVL_FOUR_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS	\
		(I2S_FIFO_ATN_LVL_EIGHT_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS	\
		(I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)

/*
 * I2S_I2S_PCM_CTRL_0
 */
#define I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ		0
#define I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ 		1
#define I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ		2
#define I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ			3
#define I2S_PCM_TRM_EDGE_CTRL_SHIFT			9

#define I2S_I2S_PCM_TRM_EDGE_CTRL_MASK			\
		(3 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ		\
		(I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ	\
		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ		\
		(I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ	\
		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ		\
		(I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ	\
		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ		\
		(I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ	\
		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)

#define I2S_PCM_TRM_MASK_BITS_ZERO			0
#define I2S_PCM_TRM_MASK_BITS_ONE			1
#define I2S_PCM_TRM_MASK_BITS_TWO			2
#define I2S_PCM_TRM_MASK_BITS_THREE			3
#define I2S_PCM_TRM_MASK_BITS_FOUR			4
#define I2S_PCM_TRM_MASK_BITS_FIVE			5
#define I2S_PCM_TRM_MASK_BITS_SIX			6
#define I2S_PCM_TRM_MASK_BITS_SEVEN			7
#define I2S_PCM_TRM_MASK_BITS_SHIFT			6

#define I2S_I2S_PCM_TRM_MASK_BITS_MASK			\
		(7 << I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_ZERO			\
		(I2S_PCM_TRM_MASK_BITS_ZERO		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_ONE			\
		(I2S_PCM_TRM_MASK_BITS_ONE		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_TWO			\
		(I2S_PCM_TRM_MASK_BITS_TWO		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_THREE			\
		(I2S_PCM_TRM_MASK_BITS_THREE		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_FOUR			\
		(I2S_PCM_TRM_MASK_BITS_FOUR		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_FIVE			\
		(I2S_PCM_TRM_MASK_BITS_FIVE		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_SIX			\
		(I2S_PCM_TRM_MASK_BITS_SIX		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_TRM_MASK_BITS_SEVEN			\
		(I2S_PCM_TRM_MASK_BITS_SEVEN		\
		<< I2S_PCM_TRM_MASK_BITS_SHIFT)

#define I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL			(1<<5)
#define I2S_I2S_PCM_CTRL_TRM_MODE			(1<<4)

#define I2S_PCM_RCV_MASK_BITS_ZERO			0
#define I2S_PCM_RCV_MASK_BITS_ONE			1
#define I2S_PCM_RCV_MASK_BITS_TWO			2
#define I2S_PCM_RCV_MASK_BITS_THREE			3
#define I2S_PCM_RCV_MASK_BITS_FOUR			4
#define I2S_PCM_RCV_MASK_BITS_FIVE			5
#define I2S_PCM_RCV_MASK_BITS_SIX			6
#define I2S_PCM_RCV_MASK_BITS_SEVEN			7
#define I2S_PCM_RCV_MASK_BITS_SHIFT			1

#define I2S_I2S_PCM_RCV_MASK_BITS_MASK			\
		(7 << I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_ZERO			\
		(I2S_PCM_RCV_MASK_BITS_ZERO		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_ONE			\
		(I2S_PCM_RCV_MASK_BITS_ONE		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_TWO			\
		(I2S_PCM_RCV_MASK_BITS_TWO		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_THREE			\
		(I2S_PCM_RCV_MASK_BITS_THREE		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_FOUR			\
		(I2S_PCM_RCV_MASK_BITS_FOUR		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_FIVE			\
		(I2S_PCM_RCV_MASK_BITS_FIVE		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_SIX			\
		(I2S_PCM_RCV_MASK_BITS_SIX		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
#define I2S_I2S_PCM_RCV_MASK_BITS_SEVEN			\
		(I2S_PCM_RCV_MASK_BITS_SEVEN		\
		<< I2S_PCM_RCV_MASK_BITS_SHIFT)

#define I2S_I2S_PCM_CTRL_RCV_MODE			(1<<0)

/*
 * I2S_TDM_CTRL_0
 */
#define I2S_TDM_CTRL_TDM_EN				 (1<<31)
#define I2S_TDM_CTRL_TX_MSB_LSB_MASK		(1<<25)
#define I2S_TDM_CTRL_TX_MSB_LSB_SHIFT	   25
#define I2S_TDM_CTRL_RX_MSB_LSB_MASK		(1<<24)
#define I2S_TDM_CTRL_RX_MSB_LSB_SHIFT	   24
#define I2S_TDM_CTRL_TDM_EDGE_CTRL_MASK	 (1<<22)
#define I2S_TDM_CTRL_TDM_EDGE_CTRL_SHIFT	22
#define I2S_TDM_CTRL_TOTAL_SLOTS_MASK	   (0x7<<18)
#define I2S_TDM_CTRL_TOTAL_SLOTS_SHIFT	  18
#define I2S_TDM_CTRL_TDM_BIT_SIZE_MASK	  (0x1f<<12)
#define I2S_TDM_CTRL_TDM_BIT_SIZE_SHIFT	 12
#define I2S_TDM_CTRL_RX_DATA_OFFSET_MASK	(0x3<<8)
#define I2S_TDM_CTRL_RX_DATA_OFFSET_SHIFT   8
#define I2S_TDM_CTRL_TX_DATA_OFFSET_MASK	(0x3<<6)
#define I2S_TDM_CTRL_TX_DATA_OFFSET_SHIFT   6
#define I2S_TDM_CTRL_FSYNC_WIDTH_MASK	   0x3f
#define I2S_TDM_CTRL_FSYNC_WIDTH_SHIFT	  0

/*
 * I2S_TDM_TX_RX_CTRL_0
 */
#define I2S_TDM_TX_RX_CTRL_TDM_TX_EN				  (1<<31)
#define I2S_TDM_TX_RX_CTRL_TDM_RX_EN				  (1<<29)
#define I2S_TDM_TX_RX_CTRL_TDM_RX_SLOT_ENABLES_MASK   (0xff<<8)
#define I2S_TDM_TX_RX_CTRL_TDM_RX_SLOT_ENABLES_SHIFT  8
#define I2S_TDM_TX_RX_CTRL_TDM_TX_SLOT_ENABLES_MASK   (0xff<<0)
#define I2S_TDM_TX_RX_CTRL_TDM_TX_SLOT_ENABLES_SHIFT  0
#define I2S_TDM_TX_FIFO_BUSY			  (1<<30)
#define I2S_TDM_RX_FIFO_BUSY			  (1<<28)


/*
 * API
 */
int i2s_set_fifo_mode(int ifc, int fifo, int tx);
int i2s_set_fifo_format(int ifc, unsigned fmt);
int i2s_set_pcm_edge_mode(int ifc, unsigned edge_mode);
int i2s_set_pcm_mask_bits(int ifc, unsigned mask_bits, int tx);
int i2s_set_pcm_fsync_width(int ifc, int fsync_long);
int i2s_enable_pcm_mode(int ifc, int enable);
int i2s_enable_fifos(int ifc, int on);

/* I2S TDM APIs */

int i2s_tdm_set_transfer(int ifc, int mode , int on);
int i2s_tdm_set_fifo_attention(int ifc, int fifo_mode, int buffersize);
u32 i2s_tdm_get_status(int ifc, int mode);
int i2s_tdm_enable(int ifc);
int i2s_tdm_set_msb_first(int ifc, int mode, int msb_first);
int i2s_tdm_set_tdm_edge_ctrl_highz(int ifc, int highz);
int i2s_tdm_set_total_slots(int ifc, int num_slots);
int i2s_tdm_set_bit_size(int ifc, int bit_size);
int i2s_tdm_set_data_offset(int ifc, int mode, int data_offset);
int i2s_tdm_set_fsync_width(int ifc, int fsync_width);
int i2s_tdm_set_slot_enables(int ifc, int mode, int slot_mask);
int i2s_tdm_init(int ifc, struct tegra_i2s_property *pi2sprop);

#endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */