/*
 * Copyright (c) 2009 NVIDIA Corporation.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * Neither the name of the NVIDIA Corporation nor the names of its contributors
 * may be used to endorse or promote products derived from this software
 * without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 *
 */
 
#ifndef PCF50626_SUPPLY_INFO_TABLE_HEADER
#define PCF50626_SUPPLY_INFO_TABLE_HEADER

#include "nvodm_pmu_pcf50626_supply_info.h"
#include "pcf50626_reg.h"


// defines for the request Voltage. This is board specific and ODM should change this based on 
// device.
#define PCF50626_REQUESTVOLTAGE_DCD1_MV       1200
#define PCF50626_REQUESTVOLTAGE_DCD2_MV       1925
#define PCF50626_REQUESTVOLTAGE_DCUD_MV       4975
#define PCF50626_REQUESTVOLTAGE_RF1REG_MV     2800
#define PCF50626_REQUESTVOLTAGE_RF2REG_MV     2800
#define PCF50626_REQUESTVOLTAGE_RF3REG_MV     1800
#define PCF50626_REQUESTVOLTAGE_RF4REG_MV     2800
#define PCF50626_REQUESTVOLTAGE_D1REG_MV      3300
#define PCF50626_REQUESTVOLTAGE_D2REG_MV      3300
#define PCF50626_REQUESTVOLTAGE_D3REG_MV      1200
#define PCF50626_REQUESTVOLTAGE_D4REG_MV      1200
#define PCF50626_REQUESTVOLTAGE_D5REG_MV      1800
#define PCF50626_REQUESTVOLTAGE_D6REG_MV      2800
#define PCF50626_REQUESTVOLTAGE_D7REG_MV      2800
#define PCF50626_REQUESTVOLTAGE_D8REG_MV      3100
#define PCF50626_REQUESTVOLTAGE_HCREG_MV      2800
#define PCF50626_REQUESTVOLTAGE_IOREG_MV      1800
#define PCF50626_REQUESTVOLTAGE_USIMREG_MV    3000
#define PCF50626_REQUESTVOLTAGE_USBREG_MV     2800
#define PCF50626_REQUESTVOLTAGE_LCREG_MV      1200

// defines for the additional load-dependent TurnOn delays. This is board
// specific and ODM should change this based on device.
#define PCF50626_TURNON_DELAY_DCD1_US       0
#define PCF50626_TURNON_DELAY_DCD2_US       0
#define PCF50626_TURNON_DELAY_DCUD_US       0
#define PCF50626_TURNON_DELAY_RF1REG_US     0
#define PCF50626_TURNON_DELAY_RF2REG_US     0
#define PCF50626_TURNON_DELAY_RF3REG_US     0
#define PCF50626_TURNON_DELAY_RF4REG_US     0
#define PCF50626_TURNON_DELAY_D1REG_US      0
#define PCF50626_TURNON_DELAY_D2REG_US      0
#define PCF50626_TURNON_DELAY_D3REG_US      0
#define PCF50626_TURNON_DELAY_D4REG_US      0
#define PCF50626_TURNON_DELAY_D5REG_US      2000
#define PCF50626_TURNON_DELAY_D6REG_US      500
#define PCF50626_TURNON_DELAY_D7REG_US      0
#define PCF50626_TURNON_DELAY_D8REG_US      0
#define PCF50626_TURNON_DELAY_HCREG_US      0
#define PCF50626_TURNON_DELAY_IOREG_US      0
#define PCF50626_TURNON_DELAY_USIMREG_US    0
#define PCF50626_TURNON_DELAY_USBREG_US     0
#define PCF50626_TURNON_DELAY_LCREG_US      0


const PCF50626PmuSupplyInfo pcf50626SupplyInfoTable[] =
{
    {
        PCF50626PmuSupply_Invalid,
        PCF50626PmuSupply_Invalid,
        0,0,0,0,   
        0,0,0,0,
        {NV_TRUE,0,0,0,0},
        0,0,0
    },

     // DCD1
    {
        PCF50626PmuSupply_DCD1,
        PCF50626PmuSupply_VBAT,
        
        PCF50626_DCD1C1_ADDR,
        PCF50626_DCD1C2_ADDR,
        PCF50626_DCD1C3_ADDR,
        PCF50626_DCD1C4_ADDR,
   
        PCF50626_DCD1DVM1_ADDR,
        PCF50626_DCD1DVM2_ADDR,
        PCF50626_DCD1DVM3_ADDR,
        PCF50626_DCD1DVMTIM_ADDR,

        {
            NV_FALSE,
            PCF50626_DCDXOUT_VOLTAGE_MIN_MV, 
            PCF50626_DCDXOUT_VOLTAGE_STEP_MV,
            PCF50626_DCDXOUT_VOLTAGE_MAX_MV,       
            PCF50626_REQUESTVOLTAGE_DCD1_MV
        },

        PCF50626_DCDXOUT_VOLTAGE_OFFSET_MV,
        PCF50626_DCDXOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_DCD1_US,
        PCF50626_DCDXOUT_SWITCH_TIME_MICROSEC
    },

    //DCD2
    {
        PCF50626PmuSupply_DCD2,
        PCF50626PmuSupply_VBAT,
        
        PCF50626_DCD2C1_ADDR,
        PCF50626_DCD2C2_ADDR,
        PCF50626_DCD2C3_ADDR,
        PCF50626_DCD2C4_ADDR,
    
        PCF50626_DCD2DVM1_ADDR,
        PCF50626_DCD2DVM2_ADDR,
        PCF50626_DCD2DVM3_ADDR,
        PCF50626_DCD2DVMTIM_ADDR,

        {
            NV_FALSE,
            PCF50626_DCDXOUT_VOLTAGE_MIN_MV, 
            PCF50626_DCDXOUT_VOLTAGE_STEP_MV,
            PCF50626_DCDXOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_DCD2_MV
        },

        PCF50626_DCDXOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DCDXOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_DCD2_US,
        PCF50626_DCDXOUT_SWITCH_TIME_MICROSEC
    },

    //DCUD
    {
        PCF50626PmuSupply_DCUD,
        PCF50626PmuSupply_VBAT,

        PCF50626_DCUDC1_ADDR,
        PCF50626_DCUDC2_ADDR,
        PCF50626_DCUDC3_ADDR,
        PCF50626_DCUDC4_ADDR,
        0,0,0,
        PCF50626_DCUDDVMTIM_ADDR,

        {
            NV_FALSE,
            PCF50626_DCUDOUT_MODE1_VOLTAGE_MIN_MV, 
            PCF50626_DCUDOUT_MODE1_VOLTAGE_STEP_MV, 
            PCF50626_DCUDOUT_MODE1_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_DCUD_MV
        },

        PCF50626_DCUDOUT_MODE1_VOLTAGE_OFFSET_MV, 
        PCF50626_DCUDOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_DCUD_US,
        PCF50626_DCUDOUT_SWITCH_TIME_MICROSEC
    },

    //DCULED            
    {
        PCF50626PmuSupply_DCULED,
        PCF50626PmuSupply_VBAT,

        PCF50626_DCULEDC1_ADDR,
        PCF50626_DCULEDC2_ADDR,
        PCF50626_DCULEDC3_ADDR,
        PCF50626_DCULED_DIMMAN_ADDR,
        0,0,0,0,
        {NV_TRUE, 0,0,0, 0},
        0,87,0
    },        

    //RF1    
    {
        PCF50626PmuSupply_RF1REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_RF1REGC1_ADDR,
        PCF50626_RF1REGC2_ADDR,
        PCF50626_RF1REGC3_ADDR,
        0,
        0,0,0,0,
        {
            NV_FALSE,
            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_RF1REG_MV
        }, 

        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF1REG_US,
        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
    },

    //RF2
    {
        PCF50626PmuSupply_RF2REG,
        PCF50626PmuSupply_VBAT,
        
        PCF50626_RF2REGC1_ADDR,
        PCF50626_RF2REGC2_ADDR,
        PCF50626_RF2REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_RF2REG_MV
        }, 

        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF2REG_US,
        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
    },

    //RF3
    {
        PCF50626PmuSupply_RF3REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_RF3REGC1_ADDR,
        PCF50626_RF3REGC2_ADDR,
        PCF50626_RF3REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_RF3REG_MV
        },
        
        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF3REG_US,
        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
    },

    //RF4
    {
        PCF50626PmuSupply_RF4REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_RF4REGC1_ADDR,
        PCF50626_RF4REGC2_ADDR,
        PCF50626_RF4REGC3_ADDR,
        0,
        0,0,0,0,
        
        {
            NV_FALSE,
            PCF50626_RFXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_RFXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_RF4REG_MV
        },

        PCF50626_RFXREGOUT_VOLTAGE_OFFSET_MV,        
        PCF50626_RFXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_RF4REG_US,
        PCF50626_RFXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D1
    {
        PCF50626PmuSupply_D1REG,            
        PCF50626PmuSupply_DCUD,
        
        PCF50626_D1REGC1_ADDR,
        PCF50626_D1REGC2_ADDR,
        PCF50626_D1REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D1REG_MV
        },

        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV,         
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D1REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D2
    {
        PCF50626PmuSupply_D2REG,
        PCF50626PmuSupply_DCUD,
        PCF50626_D2REGC1_ADDR,
        PCF50626_D2REGC2_ADDR,
        PCF50626_D2REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D2REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D2REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D3
    {
        PCF50626PmuSupply_D3REG,
        PCF50626PmuSupply_DCD2,

        PCF50626_D3REGC1_ADDR,
        PCF50626_D3REGC2_ADDR,
        PCF50626_D3REGC3_ADDR,
        0,
        0,0,0,0,
        
        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D3REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D3REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D4
    {
        PCF50626PmuSupply_D4REG,
        PCF50626PmuSupply_DCD2,

        PCF50626_D4REGC1_ADDR,
        PCF50626_D4REGC2_ADDR,
        PCF50626_D4REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D4REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D4REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D5
    {
        PCF50626PmuSupply_D5REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_D5REGC1_ADDR,
        PCF50626_D5REGC2_ADDR,
        PCF50626_D5REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D5REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D5REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D6
    {
        PCF50626PmuSupply_D6REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_D6REGC1_ADDR,
        PCF50626_D6REGC2_ADDR,
        PCF50626_D6REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D6REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D6REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D7
    {
        PCF50626PmuSupply_D7REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_D7REGC1_ADDR,
        PCF50626_D7REGC2_ADDR,
        PCF50626_D7REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D7REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D7REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //D8
    {
        PCF50626PmuSupply_D8REG,
        PCF50626PmuSupply_VBAT,

        PCF50626_D8REGC1_ADDR,
        PCF50626_D8REGC2_ADDR,
        PCF50626_D8REGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_DXREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_DXREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_DXREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_D8REG_MV
        },
        
        PCF50626_DXREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_DXREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_D8REG_US,
        PCF50626_DXREGOUT_SWITCH_TIME_MICROSEC
    },

    //HCREG
    {
        PCF50626PmuSupply_HCREG,
        PCF50626PmuSupply_VBAT,

        PCF50626_HCREGC1_ADDR,
        PCF50626_HCREGC2_ADDR,
        PCF50626_HCREGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_HCREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_HCREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_HCREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_HCREG_MV
        },
        
        PCF50626_HCREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_HCREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_HCREG_US,
        PCF50626_HCREGOUT_SWITCH_TIME_MICROSEC
    },

    //IO
    {
        PCF50626PmuSupply_IOREG,
        PCF50626PmuSupply_VBAT,

        PCF50626_IOREGC1_ADDR,
        PCF50626_IOREGC2_ADDR,
        PCF50626_IOREGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_IOREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_IOREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_IOREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_IOREG_MV
        },
        
        PCF50626_IOREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_IOREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_IOREG_US,
        PCF50626_IOREGOUT_SWITCH_TIME_MICROSEC
    },
 
    //USIM
    {
        PCF50626PmuSupply_USIMREG,
        PCF50626PmuSupply_VBAT,

        PCF50626_USIMREGC1_ADDR,
        PCF50626_USIMREGC2_ADDR,
        PCF50626_USIMREGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_USIMREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_USIMREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_USIMREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_USIMREG_MV
        },
        
        PCF50626_USIMREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_USIMREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_USIMREG_US,
        PCF50626_USIMREGOUT_SWITCH_TIME_MICROSEC
    },

    //USB
    {
        PCF50626PmuSupply_USBREG,
        PCF50626PmuSupply_VBAT,

        PCF50626_USBREGC1_ADDR,
        PCF50626_USBREGC2_ADDR,
        PCF50626_USBREGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_USBREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_USBREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_USBREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_USBREG_MV
        },
        
        PCF50626_USBREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_USBREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_USBREG_US,
        PCF50626_USBREGOUT_SWITCH_TIME_MICROSEC
    },

    //LC
    {
        PCF50626PmuSupply_LCREG,
        PCF50626PmuSupply_VBAT,

        PCF50626_LCREGC1_ADDR,
        PCF50626_LCREGC2_ADDR,
        PCF50626_LCREGC3_ADDR,
        0,
        0,0,0,0,

        {
            NV_FALSE,
            PCF50626_LCREGOUT_VOLTAGE_MIN_MV, 
            PCF50626_LCREGOUT_VOLTAGE_STEP_MV, 
            PCF50626_LCREGOUT_VOLTAGE_MAX_MV,
            PCF50626_REQUESTVOLTAGE_LCREG_MV
        },
        
        PCF50626_LCREGOUT_VOLTAGE_OFFSET_MV, 
        PCF50626_LCREGOUT_TURNON_TIME_MICROSEC + PCF50626_TURNON_DELAY_LCREG_US,
        PCF50626_LCREGOUT_SWITCH_TIME_MICROSEC
    },

    //VBAT
    {
        PCF50626PmuSupply_VBAT,
        PCF50626PmuSupply_Invalid,

        0,0,0,0,
        0,0,0,0,
        
        {NV_TRUE,0,0,0,0},
        0,0,0
    }
};

#define PCF50626SUPPLYINFOTABLESIZE NV_ARRAY_SIZE(pcf50626SupplyInfoTable)

#endif //PCF50626_VOLTAGE_INFO_TABLE_HEADER