/*
 * Copyright 2018 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/*
 * This dtsi is used by dom0 mainly for passthrough devices to domu.
 */
/ {
	/delete-node/ thermal-zones;

	/delete-node/ wu;

	edma00: dma-controller0@5a2c0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
		      <0x0 0x5a2d0000 0x0 0x10000>; /* channel13 UART0 tx */
		#dma-cells = <3>;
		dma-channels = <2>;
		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx";
		fsl,sc_rsrc_id = <SC_R_DMA_0_CH12>,
				 <SC_R_DMA_0_CH13>;
		status = "okay";
	};

	edma01: dma-controller1@5a2e0000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */
		      <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */
		#dma-cells = <3>;
		dma-channels = <2>;
		interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx";
		fsl,sc_rsrc_id = <SC_R_DMA_0_CH14>,
				 <SC_R_DMA_0_CH15>;
		status = "okay";
	};

	edma02: dma-controller2@5a300000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */
		      <0x0 0x5a310000 0x0 0x10000>; /* channel17 UART2 tx */
		#dma-cells = <3>;
		dma-channels = <2>;
		interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma0-chan16-rx", "edma0-chan17-tx";
		fsl,sc_rsrc_id = <SC_R_DMA_0_CH16>,
				 <SC_R_DMA_0_CH17>;
		status = "okay";
	};

	edma03: dma-controller3@5a320000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */
		      <0x0 0x5a330000 0x0 0x10000>; /* channel19 UART3 tx */
		#dma-cells = <3>;
		dma-channels = <2>;
		interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma0-chan18-rx", "edma0-chan19-tx";
		fsl,sc_rsrc_id = <SC_R_DMA_0_CH18>,
				 <SC_R_DMA_0_CH19>;
		status = "okay";
	};

	edma04: dma-controller4@5a340000 {
		compatible = "fsl,imx8qm-edma";
		reg = <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
		      <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
		#dma-cells = <3>;
		dma-channels = <2>;
		interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma0-chan20-rx", "edma0-chan21-tx";
		fsl,sc_rsrc_id = <SC_R_DMA_0_CH20>,
				 <SC_R_DMA_0_CH21>;
		status = "okay";
	};

	edma20: dma-controller@59200000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */
			<0x0 0x59210000 0x0 0x10000>,
			<0x0 0x59220000 0x0 0x10000>,
			<0x0 0x59230000 0x0 0x10000>,
			<0x0 0x59240000 0x0 0x10000>,
			<0x0 0x59250000 0x0 0x10000>;
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <6>;
		interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */
				<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */
				"edma2-chan2-rx", "edma2-chan3-tx",
				"edma2-chan4-tx", "edma2-chan5-tx";
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH0>,
				 <SC_R_DMA_2_CH1>,
				 <SC_R_DMA_2_CH2>,
				 <SC_R_DMA_2_CH3>,
				 <SC_R_DMA_2_CH4>,
				 <SC_R_DMA_2_CH5>;
		status = "okay";
	};

	edma21: dma-controller@0x59260000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */
		      <0x0 0x59270000 0x0 0x10000>; /* esai0 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <2>;
		interrupts = <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */
			     <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan6-rx", "edma2-chan7-tx"; /* esai0 */
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH6>,
				 <SC_R_DMA_2_CH7>;
		status = "okay";
	};

	edma22: dma-controller@0x59280000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
		      <0x0 0x59290000 0x0 0x10000>; /* spdif0 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <2>;
		interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
			     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx"; /* spdif0 */
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH8>,
				 <SC_R_DMA_2_CH9>;
		status = "okay";
	};

	edma23: dma-controller@0x592a0000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */
		      <0x0 0x592B0000 0x0 0x10000>; /* spdif1 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <2>;
		interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */
			     <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan10-rx", "edma2-chan11-tx"; /* spdif1 */
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH10>,
				 <SC_R_DMA_2_CH11>;
		status = "okay";
	};

	edma24: dma-controller@0x592c0000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
		      <0x0 0x592d0000 0x0 0x10000>; /* sai0 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <2>;
		interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
			     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan12-rx", "edma2-chan13-tx"; /* sai0 */
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH12>,
				 <SC_R_DMA_2_CH13>;
		status = "okay";
	};

	edma25: dma-controller@0x592e0000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
		      <0x0 0x592f0000 0x0 0x10000>; /* sai1 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <2>;
		interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
			     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "edma2-chan14-rx", "edma2-chan15-tx"; /* sai1 */
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH14>,
				 <SC_R_DMA_2_CH15>;
		status = "okay";
	};

	edma26: dma-controller@0x59320000 {
		compatible = "fsl,imx8qm-adma";
		reg = <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */
		      <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */
		#dma-cells = <3>;
		shared-interrupt;
		dma-channels = <2>;
		interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */
			     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */
		interrupt-names = "edma2-chan18-rx", "edma2-chan19-tx"; /* sai1 */
		fsl,sc_rsrc_id = <SC_R_DMA_2_CH18>,
				 <SC_R_DMA_2_CH19>;
		status = "okay";
	};

	usbotg1_lpcg: usbotg1_lpcg@5b270000 {
		compatible = "fsl,imx8qm-usbotg1-lpcg";
		reg = <0x0 0x5b270000 0x0 0x10000>;
	};

	usbotg3_lpcg: usbotg3_lpcg@5b280000 {
		reg = <0x0 0x5b280000 0x0 0x1000>;
	};

	sdhc1_lpcg: sdhc1_lpcg@5b200000 {
		compatible = "fsl,imx8qm-lpuart-lpcg";
		reg = <0x0 0x5b200000 0x0 0x10000>;
	};

	lpuart1_lpcg: lpcg@5a470000 {
		compatible = "fsl,imx8qm-lpuart-lpcg";
		reg = <0x0 0x5a470000 0x0 0x10000>;
	};

	lpuart2_lpcg: lpcg@5a480000 {
		compatible = "fsl,imx8qm-lpuart-lpcg";
		reg = <0x0 0x5a480000 0x0 0x10000>;
	};

	di_lvds0_lpcg: lpcg@56243000 {
		compatible = "fsl,imx8qm-di-lvds0-lpcg";
		reg = <0x0 0x56243000 0x0 0x1000>;
	};

	di_lvds1_lpcg: lpcg@57243000 {
		compatible = "fsl,imx8qm-di-lvds1-lpcg";
		reg = <0x0 0x57243000 0x0 0x1000>;
	};

	dc_0_lpcg: lpcg@56010000 {
		compatible = "fsl,imx8qm-dc0-lpcg";
		reg = <0x0 0x56010000 0x0 0x10000>;
	};

	dc_1_lpcg: lpcg@57010000 {
		compatible = "fsl,imx8qm-dc1-lpcg";
		reg = <0x0 0x57010000 0x0 0x10000>;
	};

	mu_5_lpcg: lpcg@5d600000 {
		compatible = "fsl,imx8qm-mu-lpcg";
		reg = <0x0 0x5d600000 0x0 0x10000>;
	};

	mu_6_lpcg: lpcg@5d610000 {
		compatible = "fsl,imx8qm-mu-lpcg";
		reg = <0x0 0x5d610000 0x0 0x10000>;
	};

	mu_5_lpcg_b: lpcg@5d690000 {
		compatible = "fsl,imx8qm-mu-lpcg";
		reg = <0x0 0x5d690000 0x0 0x10000>;
	};

	mu_6_lpcg_b: lpcg@5d6a0000 {
		compatible = "fsl,imx8qm-mu-lpcg";
		reg = <0x0 0x5d6a0000 0x0 0x10000>;
	};

	mu_7_lpcg_b: lpcg@5d6b0000 {
		compatible = "fsl,imx8qm-mu-lpcg";
		reg = <0x0 0x5d6b0000 0x0 0x10000>;
	};

	hsio_pcie_x2_lpcg: hsio_pcie_x2_lpcg@5f050000 {
		reg = <0x0 0x5f050000 0x0 0x10000>;
	};

	hsio_pcie_x1_lpcg: hsio_pcie_x1_lpcg@5f060000 {
		reg = <0x0 0x5f060000 0x0 0x10000>;
	};

	hsio_phy_x2_lpcg: hsio_phy_x2_lpcg@5f080000 {
		reg = <0x0 0x5f080000 0x0 0x10000>;
	};

	hsio_pcie_x2_crr2_lpcg: hsio_phy_x2_lpcg@5f0c0000 {
		reg = <0x0 0x5f0c0000 0x0 0x10000>;
	};

	mipi_csi_0_lpcg: mipi_csi_0_lpcg@58223000 {
		reg = <0x0 0x58223000 0x0 0x1000>;
	};

	img_pxl_link_csi0_lpcg: img_pxl_link_csi0_lpcg@58580000 {
		reg = <0x0 0x58580000 0x0 0x1000>;
	};

	img_pdma_0_lpcg: img_pdma_0_lpcg@58500000 {
		reg = <0x0 0x58500000 0x0 0x1000>;
	};

	img_pdma_1_lpcg: img_pdma_1_lpcg@58510000 {
		reg = <0x0 0x58510000 0x0 0x1000>;
	};

	img_pdma_2_lpcg: img_pdma_2_lpcg@58520000 {
		reg = <0x0 0x58520000 0x0 0x1000>;
	};

	img_pdma_3_lpcg: img_pdma_3_lpcg@58530000 {
		reg = <0x0 0x58530000 0x0 0x1000>;
	};

	vpu_decoder_csr: vpu_decoder_csr@0x2d080000 {
		reg = <0x0 0x2d080000 0x0 0x1000>;
	};

	/* hdmi */
	di_hdmi_lpcg: di_hdmi_lpcg@0x56263000 {
		reg = <0x0 0x56263000 0x0 0x1000>;
	};

	rx_hdmi_lpcg: rx_hdmi_lpcg@0x58263000 {
		reg = <0x0 0x58263000 0x0 0x1000>;
	};

	img_pxl_link_hdmi_lpcg: img_pxl_link_hdmi_lpcg@0x585a0000 {
		reg = <0x0 0x585a0000 0x0 0x1000>;
	};

	aud_hdmi_rx_sai_0_lpcg: aud_hdmi_rx_sai_0_lpcg@0x59480000 {
		reg = <0x0 0x59480000 0x0 0x1000>;
	};

	aud_hdmi_tx_sai_0_lpcg: aud_hdmi_tx_sai_0_lpcg@0x59490000 {
		reg = <0x0 0x59490000 0x0 0x1000>;
	};

	aud_asrc_0_lpcg: aud_asrc_0_lpcg@0x59400000 {
		reg = <0x0 0x59400000 0x0 0x1000>;
	};

	aud_esai_0_lpcg: aud_esai_0_lpcg@0x59410000 {
		reg = <0x0 0x59410000 0x0 0x1000>;
	};

	aud_pll_clk0_lpcg: aud_pll_clk0_lpcg {
		reg = <0x0 0x59d20000 0x0 0x1000>;
	};

	aud_pll_clk1_lpcg: aud_pll_clk1_lpcg {
		reg = <0x0 0x59d30000 0x0 0x1000>;
	};

	aud_mclkout0_lpcg: aud_mclkout0_lpcg {
		reg = <0x0 0x59d50000 0x0 0x1000>;
	};

	aud_mclkout1_lpcg: aud_mclkout1_lpcg {
		reg = <0x0 0x59d60000 0x0 0x1000>;
	};

	aud_rec_clk0_lpcg: aud_rec_clk0_lpcg {
		reg = <0x0 0x59d00000 0x0 0x1000>;
	};

	aud_rec_clk1_lpcg: aud_rec_clk1_lpcg {
		reg = <0x0 0x59d10000 0x0 0x1000>;
	};

	aud_dsp_lpcg: aud_dsp_lpcg {
		reg = <0x0 0x59580000 0x0 0x1000>;
	};
	aud_ocram_lpcg: aud_ocram_lpcg {
		reg = <0x0 0x59590000 0x0 0x1000>;
	};

	aud_sai_0_lpcg: aud_sai_0_lpcg {
		reg = <0x0 0x59440000 0x0 0x1000>;
	};
};

/delete-node/ &edma0;
/delete-node/ &edma2;

&mu {
	interrupt-parent = <&gic>;
};

&flexcan1 {
	interrupt-parent = <&gic>;
};

&flexcan2 {
	interrupt-parent = <&gic>;
};

&flexcan3 {
	interrupt-parent = <&gic>;
};

&lpuart0 {
	interrupt-parent = <&gic>;
};

&lpuart1 {
	interrupt-parent = <&gic>;
	dmas = <&edma01 15 0 0>, <&edma01 14 0 1>;
};

&lpuart2 {
	interrupt-parent = <&gic>;
	dmas = <&edma02 17 0 0>, <&edma02 16 0 1>;
};

&lpuart3 {
	interrupt-parent = <&gic>;
	dmas = <&edma03 19 0 0>, <&edma03 18 0 1>;
};

&lpuart4 {
	interrupt-parent = <&gic>;
	dmas = <&edma04 21 0 0>, <&edma04 20 0 1>;
};

&usdhc1 {
	/delete-property/ iommus;
};

&usdhc2 {
	/delete-property/ iommus;
};

&usdhc3 {
	/delete-property/ iommus;
};

&fec1 {
	interrupt-parent = <&gic>;
	/delete-property/ iommus;
};

&fec2 {
	interrupt-parent = <&gic>;
	/delete-property/ iommus;
};

&sata {
	/delete-property/ iommus;
};

&usbotg1 {
	interrupt-parent = <&gic>;
};

&usbh1 {
	interrupt-parent = <&gic>;
};

&usbotg3 {
	interrupt-parent = <&gic>;
};

&smmu {
	/* xen only supports legacy bindings for now */
	#iommu-cells = <0>;
};

&dpu1 {
	fsl,sc_rsrc_id = <SC_R_DC_0_BLIT0>,
			 <SC_R_DC_0_BLIT1>,
			 <SC_R_DC_0_BLIT2>,
			 <SC_R_DC_0_BLIT_OUT>,
			 <SC_R_DC_0_WARP>,
			 <SC_R_DC_0_VIDEO0>,
			 <SC_R_DC_0_VIDEO1>,
			 <SC_R_DC_0_FRAC0>,
			 <SC_R_DC_0>;
};

&dpu2 {
	fsl,sc_rsrc_id = <SC_R_DC_1_BLIT0>,
			 <SC_R_DC_1_BLIT1>,
			 <SC_R_DC_1_BLIT2>,
			 <SC_R_DC_1_BLIT_OUT>,
			 <SC_R_DC_1_WARP>,
			 <SC_R_DC_1_VIDEO0>,
			 <SC_R_DC_1_VIDEO1>,
			 <SC_R_DC_1_FRAC0>,
			 <SC_R_DC_1>;
};

&esai0 {
	dmas = <&edma21 6 0 1>, <&edma21 7 0 0>;
};

&spdif0 {
	dmas = <&edma22 8 0 5>, <&edma22 9 0 4>;
};

&spdif1 {
	dmas = <&edma23 10 0 5>, <&edma23 11 0 4>;
};

&sai0 {
	dmas = <&edma24 12 0 1>, <&edma24 13 0 0>;
};

&sai1 {
	dmas = <&edma25 14 0 1>, <&edma25 15 0 0>;
};

/delete-node/ &sai2;
/delete-node/ &sai3;

&sai_hdmi_rx {
	dmas = <&edma26 18 0 1>;
};

&sai_hdmi_tx {
	dmas = <&edma26 19 0 0>;
};

&asrc0 {
	dmas = <&edma20 0 0 0>, <&edma20 1 0 0>, <&edma20 2 0 0>,
	       <&edma20 3 0 1>, <&edma20 4 0 1>, <&edma20 5 0 1>;
};