/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fsl-imx8-ca53.dtsi"
#include "fsl-imx8-ca72.dtsi"
#include <dt-bindings/clock/imx8qm-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <dt-bindings/soc/imx8_hsio.h>
#include <dt-bindings/soc/imx8_pd.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,imx8qm";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		csi0 = &mipi_csi_0;
		csi1 = &mipi_csi_1;
		dpu0 = &dpu1;
		dpu1 = &dpu2;
		ethernet0 = &fec1;
		ethernet1 = &fec2;
		dsi_phy0 = &mipi_dsi_phy1;
		dsi_phy1 = &mipi_dsi_phy2;
		mipi_dsi0 = &mipi_dsi1;
		mipi_dsi1 = &mipi_dsi2;
		ldb0 = &ldb1;
		ldb1 = &ldb2;
		isi0 = &isi_0;
		isi1 = &isi_1;
		isi2 = &isi_2;
		isi3 = &isi_3;
		isi4 = &isi_4;
		isi5 = &isi_5;
		isi6 = &isi_6;
		isi7 = &isi_7;
		serial0 = &lpuart0;
		serial1 = &lpuart1;
		serial2 = &lpuart2;
		serial3 = &lpuart3;
		serial4 = &lpuart4;
		mmc0 = &usdhc1;
		mmc1 = &usdhc2;
		mmc2 = &usdhc3;
		usbphy0 = &usbphy1;
		can0 = &flexcan1;
		can1 = &flexcan2;
		can2 = &flexcan3;
		i2c0 = &i2c_rpbus_0;
		i2c1 = &i2c_rpbus_1;
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
		      /* DRAM space - 1, size : 1 GB DRAM */
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * reserved-memory layout
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */

		decoder_boot: decoder_boot@0x84000000 {
			no-map;
			reg = <0 0x84000000 0 0x2000000>;
		};
		encoder_boot: encoder_boot@0x86000000 {
			no-map;
			reg = <0 0x86000000 0 0x400000>;
		};
		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90000000 0 0x400000>;
		};
		rpmsg_dma_reserved:rpmsg_dma@0x90400000 {
			compatible = "shared-dma-pool";
			no-map;
			reg = <0 0x90400000 0 0x1C00000>;
		};
		decoder_rpc: decoder_rpc@0x92000000 {
			no-map;
			reg = <0 0x92000000 0 0x200000>;
		};
		encoder_rpc: encoder_rpc@0x92200000 {
			no-map;
			reg = <0 0x92200000 0 0x200000>;
		};
		dsp_reserved: dsp@0x92400000 {
			no-map;
			reg = <0 0x92400000 0 0x2000000>;
		};
		encoder_reserved: encoder_reserved@0x94400000 {
			no-map;
			reg = <0 0x94400000 0 0x800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x3c000000>;
			alloc-ranges = <0 0x96000000 0 0x3c000000>;
			linux,cma-default;
		};

	};

	gic: interrupt-controller@51a00000 {
		compatible = "arm,gic-v3";
		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
		      <0x0 0x51b00000 0 0xC0000>, /* GICR */
		      <0x0 0x52000000 0 0x2000>,  /* GICC */
		      <0x0 0x52010000 0 0x1000>,  /* GICH */
		      <0x0 0x52020000 0 0x20000>; /* GICV */
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
		interrupt-parent = <&gic>;
	};

	mu: mu@5d1c0000 {
		compatible = "fsl,imx8-mu";
		reg = <0x0 0x5d1c0000 0x0 0x10000>;
		interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
		fsl,scu_ap_mu_id = <0>;
		status = "okay";
	};

	mu13: mu13@5d280000 {
		compatible = "fsl,imx8-mu-dsp";
		reg = <0x0 0x5d280000 0x0 0x10000>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		fsl,dsp_ap_mu_id = <13>;
		status = "okay";
	};

	mu_m0: mu_m0@2d000000 {
		compatible = "fsl,imx8-mu0-vpu-m0";
		reg = <0x0 0x2d000000 0x0 0x20000>;
		interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <16>;
		status = "okay";
	};

	mu1_m0: mu1_m0@2d020000 {
		compatible = "fsl,imx8-mu1-vpu-m0";
		reg = <0x0 0x2d020000 0x0 0x20000>;
		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <17>;
		status = "okay";
	};

	mu2_m0: mu2_m0@2d040000 {
		compatible = "fsl,imx8-mu2-vpu-m0";
		reg = <0x0 0x2d040000 0x0 0x20000>;
		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		fsl,vpu_ap_mu_id = <18>;
		status = "okay";
	};

	vpu_decoder: vpu_decoder@2c000000 {
		compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec";
		boot-region = <&decoder_boot>;
		rpc-region = <&decoder_rpc>;
		reg = <0x0 0x2c000000 0x0 0x1000000>;
		reg-names = "vpu_regs";
		reg-csr = <0x2d080000>;
		power-domains = <&pd_vpu_dec>;
		status = "disabled";
	};

	vpu_encoder: vpu_encoder@2d000000 {
		compatible = "nxp,imx8qm-b0-vpuenc";
		#address-cells = <1>;
		#size-cells = <1>;

		boot-region = <&encoder_boot>;
		rpc-region = <&encoder_rpc>;
		reserved-region = <&encoder_reserved>;
		reg = <0x0 0x2d000000 0x0 0x1000000>,	/*VPU Encoder*/
			<0x0 0x2c000000 0x0 0x2000000>; /*VPU*/
		reg-names = "vpu_regs";
		power-domains = <&pd_vpu_enc>;
		reg-rpc-system = <0x40000000>;

		resolution-max = <1920 1080>;
		fps-max = <120>;
		status = "disabled";

		core0@1020000 {
			compatible = "fsl,imx8-mu1-vpu-m0";
			reg = <0x1020000 0x20000>;
			reg-csr = <0x1090000 0x10000>;
			interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
			fsl,vpu_ap_mu_id = <17>;
			fw-buf-size = <0x200000>;
			rpc-buf-size = <0x80000>;
			print-buf-size = <0x80000>;
		};
		core1@1040000 {
			compatible = "fsl,imx8-mu2-vpu-m0";
			reg = <0x1040000 0x20000>;
			reg-csr = <0x10a0000 0x10000>;
			interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
			fsl,vpu_ap_mu_id = <18>;
			fw-buf-size = <0x200000>;
			rpc-buf-size = <0x80000>;
			print-buf-size = <0x80000>;
		};
	};

	clk: clk {
		compatible = "fsl,imx8qm-clk";
		#clock-cells = <1>;
	};

	iomuxc: iomuxc {
		compatible = "fsl,imx8qm-iomuxc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
		clock-frequency = <8000000>;
		interrupt-parent = <&gic>;
	};

	smmu: iommu@51400000 {
		compatible = "arm,mmu-500";
		interrupt-parent = <&gic>;
		reg = <0 0x51400000 0 0x40000>;
		#global-interrupts = <1>;
		#iommu-cells = <2>;
		interrupts = <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
			     <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
	};

	cci: cci@52090000 {
		compatible = "arm,cci-400";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0 0x52090000 0 0x1000>;
		ranges = <0 0 0x52090000 0x10000>;

		pmu@9000 {
			compatible = "arm,cci-400-pmu,r1",
				     "arm,cci-400-pmu";
			reg = <0x9000 0x4000>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&gic>;
		};
	};

	#include "fsl-imx8qm-device.dtsi"
};

&A53_0 {
	operating-points = <
		/* kHz    uV */
		/* voltage is maintained by SCFW, so no need here */
		1200000	   0
		1104000	   0
		900000	   0
		600000	   0
	>;
	clocks = <&clk IMX8QM_A53_DIV>;
	clock-latency = <61036>;
	#cooling-cells = <2>;
	/delete-property/ cpu-idle-states;
};

&A72_0 {
	operating-points = <
		/* kHz    uV */
		/* voltage is maintained by SCFW, so no need here */
		1596000	   0
		1296000	   0
		1056000	   0
		600000     0
	>;
	clocks = <&clk IMX8QM_A72_DIV>;
	clock-latency = <61036>;
	#cooling-cells = <2>;
	/delete-property/ cpu-idle-states;
};


&imx8_gpu_ss {/*<freq-kHz vol-uV>*/
       operating-points = <
/*overdrive*/  800000  0  /*The first tuple is for core clock frequency*/
               1000000 0  /*The second tuple is for shader clock frequency*/
/*nominal*/    650000  0
               700000  0
/*underdrive*/ 400000  0  /*core/shader clock share the same frequency on underdrive mode*/
       >;
};

&A53_1 {
	/delete-property/ cpu-idle-states;
};

&A53_2 {
	/delete-property/ cpu-idle-states;
};

&A53_3 {
	/delete-property/ cpu-idle-states;
};

&A72_1 {
	/delete-property/ cpu-idle-states;
};