/*
 * MPC8610 HPCD Device Tree Source
 *
 * Copyright 2007-2008 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under the terms of the GNU General Public License Version 2 as published
 * by the Free Software Foundation.
 */

/dts-v1/;

/ {
	model = "MPC8610HPCD";
	compatible = "fsl,MPC8610HPCD";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &serial0;
		serial1 = &serial1;
		pci0 = &pci0;
		pci1 = &pci1;
		pci2 = &pci2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		PowerPC,8610@0 {
			device_type = "cpu";
			reg = <0>;
			d-cache-line-size = <32>;
			i-cache-line-size = <32>;
			d-cache-size = <32768>;		// L1
			i-cache-size = <32768>;		// L1
			timebase-frequency = <0>;	// From uboot
			bus-frequency = <0>;		// From uboot
			clock-frequency = <0>;		// From uboot
		};
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x20000000>;	// 512M at 0x0
	};

	board-control@e8000000 {
		compatible = "fsl,fpga-pixis";
		reg = <0xe8000000 32>;		// pixis at 0xe8000000
	};

	soc@e0000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		#interrupt-cells = <2>;
		device_type = "soc";
		compatible = "fsl,mpc8610-immr", "simple-bus";
		ranges = <0x0 0xe0000000 0x00100000>;
		reg = <0xe0000000 0x1000>;
		bus-frequency = <0>;

		i2c@3000 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <0>;
			compatible = "fsl-i2c";
			reg = <0x3000 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;

			cs4270:codec@4f {
				compatible = "cirrus,cs4270";
				reg = <0x4f>;
				/* MCLK source is a stand-alone oscillator */
				clock-frequency = <12288000>;
			};
		};

		i2c@3100 {
			#address-cells = <1>;
			#size-cells = <0>;
			cell-index = <1>;
			compatible = "fsl-i2c";
			reg = <0x3100 0x100>;
			interrupts = <43 2>;
			interrupt-parent = <&mpic>;
			dfsrr;
		};

		serial0: serial@4500 {
			cell-index = <0>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4500 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		serial1: serial@4600 {
			cell-index = <1>;
			device_type = "serial";
			compatible = "ns16550";
			reg = <0x4600 0x100>;
			clock-frequency = <0>;
			interrupts = <42 2>;
			interrupt-parent = <&mpic>;
		};

		display@2c000 {
			compatible = "fsl,diu";
			reg = <0x2c000 100>;
			interrupts = <72 2>;
			interrupt-parent = <&mpic>;
		};

		mpic: interrupt-controller@40000 {
			clock-frequency = <0>;
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <2>;
			reg = <0x40000 0x40000>;
			compatible = "chrp,open-pic";
			device_type = "open-pic";
			big-endian;
		};

		global-utilities@e0000 {
			compatible = "fsl,mpc8610-guts";
			reg = <0xe0000 0x1000>;
			fsl,has-rstcr;
		};

		i2s@16000 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <0>;
			reg = <0x16000 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <62 2>;
			fsl,mode = "i2s-slave";
			codec-handle = <&cs4270>;
		};

		ssi@16100 {
			compatible = "fsl,mpc8610-ssi";
			cell-index = <1>;
			reg = <0x16100 0x100>;
			interrupt-parent = <&mpic>;
			interrupts = <63 2>;
		};

		dma@21300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
			cell-index = <0>;
			reg = <0x21300 0x4>; /* DMA general status register */
			ranges = <0x0 0x21100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <20 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <21 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <22 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,eloplus-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <23 2>;
			};
		};

		dma@c300 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "fsl,mpc8610-dma", "fsl,mpc8540-dma";
			cell-index = <1>;
			reg = <0xc300 0x4>; /* DMA general status register */
			ranges = <0x0 0xc100 0x200>;

			dma-channel@0 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <0>;
				reg = <0x0 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <60 2>;
			};
			dma-channel@1 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <1>;
				reg = <0x80 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <61 2>;
			};
			dma-channel@2 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <2>;
				reg = <0x100 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <62 2>;
			};
			dma-channel@3 {
				compatible = "fsl,mpc8610-dma-channel",
					"fsl,mpc8540-dma-channel";
				cell-index = <3>;
				reg = <0x180 0x80>;
				interrupt-parent = <&mpic>;
				interrupts = <63 2>;
			};
		};

	};

	pci0: pci@e0008000 {
		cell-index = <0>;
		compatible = "fsl,mpc8610-pci";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe0008000 0x1000>;
		bus-range = <0 0>;
		ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <24 2>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <
			/* IDSEL 0x11 */
			0x8800 0 0 1 &mpic 4 1
			0x8800 0 0 2 &mpic 5 1
			0x8800 0 0 3 &mpic 6 1
			0x8800 0 0 4 &mpic 7 1

			/* IDSEL 0x12 */
			0x9000 0 0 1 &mpic 5 1
			0x9000 0 0 2 &mpic 6 1
			0x9000 0 0 3 &mpic 7 1
			0x9000 0 0 4 &mpic 4 1
			>;
	};

	pci1: pcie@e000a000 {
		cell-index = <1>;
		compatible = "fsl,mpc8641-pcie";
		device_type = "pci";
		#interrupt-cells = <1>;
		#size-cells = <2>;
		#address-cells = <3>;
		reg = <0xe000a000 0x1000>;
		bus-range = <1 3>;
		ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
			  0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
		clock-frequency = <33333333>;
		interrupt-parent = <&mpic>;
		interrupts = <26 2>;
		interrupt-map-mask = <0xf800 0 0 7>;

		interrupt-map = <
			/* IDSEL 0x1b */
			0xd800 0 0 1 &mpic 2 1

			/* IDSEL 0x1c*/
			0xe000 0 0 1 &mpic 1 1
			0xe000 0 0 2 &mpic 1 1
			0xe000 0 0 3 &mpic 1 1
			0xe000 0 0 4 &mpic 1 1

			/* IDSEL 0x1f */
			0xf800 0 0 1 &mpic 3 0
			0xf800 0 0 2 &mpic 0 1
		>;

		pcie@0 {
			reg = <0 0 0 0 0>;
			#size-cells = <2>;
			#address-cells = <3>;
			device_type = "pci";
			ranges = <0x02000000 0x0 0xa0000000
				  0x02000000 0x0 0xa0000000
				  0x0 0x10000000
				  0x01000000 0x0 0x00000000
				  0x01000000 0x0 0x00000000
				  0x0 0x00100000>;
			uli1575@0 {
				reg = <0 0 0 0 0>;
				#size-cells = <2>;
				#address-cells = <3>;
				ranges = <0x02000000 0x0 0xa0000000
					  0x02000000 0x0 0xa0000000
					  0x0 0x10000000
					  0x01000000 0x0 0x00000000
					  0x01000000 0x0 0x00000000
					  0x0 0x00100000>;
			};
		};
	};

	pci2: pcie@e0009000 {
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		device_type = "pci";
		compatible = "fsl,mpc8641-pcie";
		reg = <0xe0009000 0x00001000>;
		ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
		bus-range = <0 255>;
		interrupt-map-mask = <0xf800 0 0 7>;
		interrupt-map = <0x0000 0 0 1 &mpic 4 1
				 0x0000 0 0 2 &mpic 5 1
				 0x0000 0 0 3 &mpic 6 1
				 0x0000 0 0 4 &mpic 7 1>;
		interrupt-parent = <&mpic>;
		interrupts = <25 2>;
		clock-frequency = <33333333>;
	};
};