summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/armada-385-rd.dts
blob: 45250c88814b89c6b83213c7572c8896f7190e2b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
/*
 * Device Tree file for Marvell Armada 385 Reference Design board
 * (RD-88F6820-AP)
 *
 *  Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

/dts-v1/;
#include "armada-385.dtsi"

/ {
	model = "Marvell Armada 385 Reference Design";
	compatible = "marvell,a385-rd", "marvell,armada385", "marvell,armada38x";

	chosen {
		bootargs = "console=ttyS0,115200 earlyprintk";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x10000000>; /* 256 MB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;

		internal-regs {
			spi@10600 {
				status = "okay";

				spi-flash@0 {
					#address-cells = <1>;
					#size-cells = <1>;
					compatible = "st,m25p128";
					reg = <0>; /* Chip select 0 */
					spi-max-frequency = <108000000>;
				};
			};

			i2c@11000 {
				status = "okay";
				clock-frequency = <100000>;
			};

			serial@12000 {
				clock-frequency = <200000000>;
				status = "okay";
			};

			ethernet@30000 {
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
			};

			ethernet@70000 {
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
			};


			mdio {
				phy0: ethernet-phy@0 {
					reg = <0>;
				};

				phy1: ethernet-phy@1 {
					reg = <1>;
				};
			};
		};

		pcie-controller {
			status = "okay";
			/*
			 * One PCIe units is accessible through
			 * standard PCIe slot on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};
		};
	};
};