1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
|
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "imx6dl-pinfunc.h"
#include "imx6qdl.dtsi"
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
operating-points = <
/* kHz uV */
996000 1275000
792000 1175000
396000 1075000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC-PU uV */
996000 1175000
792000 1175000
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks 104>, <&clks 6>, <&clks 16>,
<&clks 17>, <&clks 170>;
clock-names = "arm", "pll2_pfd2_396m", "step",
"pll1_sw", "pll1_sys";
arm-supply = <®_arm>;
pu-supply = <®_pu>;
soc-supply = <®_soc>;
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
};
};
soc {
busfreq { /* BUSFREQ */
compatible = "fsl,imx6_busfreq";
clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
<&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 22> , <&clks 8>;
clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
"periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_sel", "pll3_pfd1_540m";
interrupts = <0 107 0x04>, <0 112 0x4>;
interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
fsl,max_ddr_freq = <400000000>;
};
gpu: gpu@00130000 {
compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu";
reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
<0x0 0x0>;
reg-names = "iobase_3d", "iobase_2d",
"phys_baseaddr";
interrupts = <0 9 0x04>, <0 10 0x04>;
interrupt-names = "irq_3d", "irq_2d";
clocks = <&clks 143>, <&clks 27>,
<&clks 121>, <&clks 122>,
<&clks 0>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
"gpu2d_clk", "gpu3d_clk",
"gpu3d_shader_clk";
resets = <&src 0>, <&src 3>;
reset-names = "gpu3d", "gpu2d";
pu-supply = <®_pu>;
};
ocram: sram@00900000 {
compatible = "mmio-sram";
reg = <0x00904000 0x1C000>;
clocks = <&clks 142>;
};
hdmi_core: hdmi_core@00120000 {
compatible = "fsl,imx6dl-hdmi-core";
reg = <0x00120000 0x9000>;
clocks = <&clks 124>, <&clks 123>;
clock-names = "hdmi_isfr", "hdmi_iahb";
status = "disabled";
};
hdmi_video: hdmi_video@020e0000 {
compatible = "fsl,imx6dl-hdmi-video";
reg = <0x020e0000 0x1000>;
reg-names = "hdmi_gpr";
interrupts = <0 115 0x04>;
clocks = <&clks 124>, <&clks 123>;
clock-names = "hdmi_isfr", "hdmi_iahb";
status = "disabled";
};
hdmi_audio: hdmi_audio@00120000 {
compatible = "fsl,imx6dl-hdmi-audio";
clocks = <&clks 124>, <&clks 123>;
clock-names = "hdmi_isfr", "hdmi_iahb";
dmas = <&sdma 2 22 0>;
dma-names = "tx";
status = "disabled";
};
hdmi_cec: hdmi_cec@00120000 {
compatible = "fsl,imx6dl-hdmi-cec";
interrupts = <0 115 0x04>;
status = "disabled";
};
aips1: aips-bus@02000000 {
vpu@02040000 {
iramsize = <0>;
status = "okay";
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
pxp: pxp@020f0000 {
compatible = "fsl,imx6dl-pxp-dma";
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
clocks = <&clks 133>;
clock-names = "pxp-axi";
status = "disabled";
};
epdc: epdc@020f4000 {
compatible = "fsl,imx6dl-epdc";
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
clocks = <&clks 133>, <&clks 137>;
clock-names = "epdc_axi", "epdc_pix";
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
};
};
aips2: aips-bus@02100000 {
mipi_dsi: mipi@021e0000 {
compatible = "fsl,imx6dl-mipi-dsi";
reg = <0x021e0000 0x4000>;
interrupts = <0 102 0x04>;
gpr = <&gpr>;
clocks = <&clks 138>, <&clks 204>;
clock-names = "mipi_pllref_clk", "mipi_cfg_clk";
status = "disabled";
};
i2c4: i2c@021f8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx1-i2c";
reg = <0x021f8000 0x4000>;
interrupts = <0 35 0x04>;
status = "disabled";
};
};
};
};
&iomuxc {
epdc {
pinctrl_epdc_0: epdcgrp-0 {
fsl,pins = <
MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000
MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000
MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000
MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000
MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000
MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000
MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000
MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000
MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000
MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000
MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000
MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000
MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000
MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000
MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000
MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000
MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000
MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000
MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000
MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000
>;
};
};
};
|
