summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/rk3188.dtsi
blob: ed9a70af3e3f88ff59a266165b2655754e50dbda (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3xxx.dtsi"
#include "rk3188-clocks.dtsi"

/ {
	compatible = "rockchip,rk3188";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			next-level-cache = <&L2>;
			reg = <0x3>;
		};
	};

	soc {
		global-timer@1013c200 {
			interrupts = <GIC_PPI 11 0xf04>;
		};

		local-timer@1013c600 {
			interrupts = <GIC_PPI 13 0xf04>;
		};

		sram: sram@10080000 {
			compatible = "mmio-sram";
			reg = <0x10080000 0x8000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x10080000 0x8000>;

			smp-sram@0 {
				compatible = "rockchip,rk3066-smp-sram";
				reg = <0x0 0x50>;
			};
		};

		pinctrl@20008000 {
			compatible = "rockchip,rk3188-pinctrl";
			reg = <0x20008000 0xa0>,
			      <0x20008164 0x1a0>;
			reg-names = "base", "pull";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			gpio0: gpio0@0x2000a000 {
				compatible = "rockchip,rk3188-gpio-bank0";
				reg = <0x2000a000 0x100>,
				      <0x20004064 0x8>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk_gates8 9>;

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio1: gpio1@0x2003c000 {
				compatible = "rockchip,gpio-bank";
				reg = <0x2003c000 0x100>;
				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk_gates8 10>;

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio2: gpio2@2003e000 {
				compatible = "rockchip,gpio-bank";
				reg = <0x2003e000 0x100>;
				interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk_gates8 11>;

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			gpio3: gpio3@20080000 {
				compatible = "rockchip,gpio-bank";
				reg = <0x20080000 0x100>;
				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clk_gates8 12>;

				gpio-controller;
				#gpio-cells = <2>;

				interrupt-controller;
				#interrupt-cells = <2>;
			};

			pcfg_pull_up: pcfg_pull_up {
				bias-pull-up;
			};

			pcfg_pull_down: pcfg_pull_down {
				bias-pull-down;
			};

			pcfg_pull_none: pcfg_pull_none {
				bias-disable;
			};

			uart0 {
				uart0_xfer: uart0-xfer {
					rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
							<RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart0_cts: uart0-cts {
					rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart0_rts: uart0-rts {
					rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			uart1 {
				uart1_xfer: uart1-xfer {
					rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
							<RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart1_cts: uart1-cts {
					rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart1_rts: uart1-rts {
					rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			uart2 {
				uart2_xfer: uart2-xfer {
					rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
							<RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
				};
				/* no rts / cts for uart2 */
			};

			uart3 {
				uart3_xfer: uart3-xfer {
					rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
							<RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart3_cts: uart3-cts {
					rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
				};

				uart3_rts: uart3-rts {
					rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			sd0 {
				sd0_clk: sd0-clk {
					rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_cmd: sd0-cmd {
					rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_cd: sd0-cd {
					rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_wp: sd0-wp {
					rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_pwr: sd0-pwr {
					rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_bus1: sd0-bus-width1 {
					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd0_bus4: sd0-bus-width4 {
					rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
				};
			};

			sd1 {
				sd1_clk: sd1-clk {
					rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_cmd: sd1-cmd {
					rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_cd: sd1-cd {
					rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_wp: sd1-wp {
					rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_bus1: sd1-bus-width1 {
					rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
				};

				sd1_bus4: sd1-bus-width4 {
					rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
							<RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
				};
			};
		};
	};
};