blob: 66029d8463a04fca2e675ec3e5ea92b69d180c63 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
|
/*
* arch/arm/mach-tegra/reset.h
*
* CPU reset dispatcher.
*
* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_TEGRA_RESET_H
#define __MACH_TEGRA_RESET_H
#define TEGRA_RESET_MASK_PRESENT 0
#define TEGRA_RESET_MASK_LP1 1
#define TEGRA_RESET_MASK_LP2 2
#define TEGRA_RESET_STARTUP_SECONDARY 3
#define TEGRA_RESET_STARTUP_LP2 4
#define TEGRA_RESET_STARTUP_LP1 5
#define TEGRA_RESET_C0_L2_TAG_LATENCY 6
#define TEGRA_RESET_C0_L2_DATA_LATENCY 7
#define TEGRA_RESET_C1_L2_TAG_LATENCY 8
#define TEGRA_RESET_C1_L2_DATA_LATENCY 9
#define TEGRA_RESET_MASK_MC_CLK 10
#define TEGRA_RESET_SECURE_FW_PRESENT 11
#define TEGRA_RESET_DATA_SIZE 12
#ifdef CONFIG_ARM64
#define RESET_DATA(x) ((TEGRA_RESET_##x)*8)
#else
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
#endif
#ifndef __ASSEMBLY__
#include <linux/cpumask.h>
extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
void __tegra_cpu_reset_handler_start(void);
void __tegra_cpu_reset_handler(void);
void __tegra_cpu_reset_handler_end(void);
void tegra_secondary_startup(void);
#ifdef CONFIG_PM_SLEEP
#define tegra_cpu_lp1_mask ((unsigned long *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
(ulong)__tegra_cpu_reset_handler_start))))
#define tegra_mc_clk_mask ((unsigned long *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_MC_CLK] - \
(ulong)__tegra_cpu_reset_handler_start))))
#define tegra_cpu_reset_handler_ptr ((u32 *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)__tegra_cpu_reset_handler_data - \
(ulong)__tegra_cpu_reset_handler_start))))
#define tegra_cpu_lp2_mask ((cpumask_t *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
(ulong)__tegra_cpu_reset_handler_start))))
#endif
#define tegra_cpu_c0_l2_tag_latency \
__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_TAG_LATENCY]
#define tegra_cpu_c0_l2_tag_latency_iram \
((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_TAG_LATENCY] \
- (ulong)__tegra_cpu_reset_handler_start))))
#define tegra_cpu_c0_l2_data_latency \
__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_DATA_LATENCY]
#define tegra_cpu_c0_l2_data_latency_iram \
((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_DATA_LATENCY] \
- (ulong)__tegra_cpu_reset_handler_start))))
#define tegra_cpu_c1_l2_tag_latency \
__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_TAG_LATENCY]
#define tegra_cpu_c1_l2_tag_latency_iram \
((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_TAG_LATENCY] \
- (ulong)__tegra_cpu_reset_handler_start))))
#define tegra_cpu_c1_l2_data_latency \
__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_DATA_LATENCY]
#define tegra_cpu_c1_l2_data_latency_iram \
((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_DATA_LATENCY] \
- (ulong)__tegra_cpu_reset_handler_start))))
#define tegra_cpu_reset_handler_offset \
((ulong)__tegra_cpu_reset_handler - \
(ulong)__tegra_cpu_reset_handler_start)
#define tegra_cpu_reset_handler_size \
(__tegra_cpu_reset_handler_end - \
__tegra_cpu_reset_handler_start)
#ifdef CONFIG_PM_SLEEP
void tegra_cpu_reset_handler_save(void);
void tegra_cpu_reset_handler_restore(void);
#endif
#endif
#endif
|
