path: root/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dts

/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "fsl-imx8qm.dtsi"

/ {
	model = "Toradex Apalis iMX8QM";
	compatible = "toradex,imx8qm-apalis", "fsl,imx8qm";

	aliases {
		rtc0 = &rtc_i2c;
		rtc1 = &rtc;
	};

	chosen {
		bootargs = "console=ttyLP1,115200 earlycon=lpuart32,0x5a070000,115200";
		stdout-path = &lpuart1;
	};

	backlight: backlight {
		compatible = "gpio-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>,  /* BKL1_ON */
			<&gpio1 10 GPIO_ACTIVE_HIGH>; /* BKL1_PWM */
		default-on;
		status = "okay";
	};

	pcie_sata_refclk: clock-generator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie_sata_refclk_gate: ref-clock {
		compatible = "gpio-gate-clock";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
		#clock-cells = <0>;
		clocks = <&pcie_sata_refclk>;
		enable-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_vref_1v8: regulator-vref-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vref-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reg_usb_host_vbus: regulator-usb-host-vbus {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usbh_en>;
		regulator-name = "usb_host_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		gpio =  <&gpio4 4 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		regulator-always-on;
	};

	gpio-fan {
		compatible = "gpio-fan";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio8>;
		gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
		gpio-fan,speed-map = <	 0 0
				      3000 1>;
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,name = "imx8qm-sgtl5000";
		simple-audio-card,format = "i2s";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,frame-master = <&dailink_master>;
		/*simple-audio-card,mclk-fs = <1>;*/
		simple-audio-card,cpu {
			sound-dai = <&sai1>;
		};

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000>;
			clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
		};
	};
};

&sai_hdmi_tx {
	assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>,
			<&clk IMX8QM_AUD_PLL0_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
			<&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>;
	assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
	assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
	fsl,sai-asynchronous;
	status = "okay";
};

&iomuxc {
	imx8qm-apalis {
		pinctrl_sgtl5000: sgtl5000grp {
			fsl,pins = <
				SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0	0xc600004c
			>;
		};

		pinctrl_cam: camgrp {
			fsl,pins = <
				SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08		0x06000021
				SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09		0x06000021
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
				SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15	0x00000021
			>;
		};

		pinctrl_gpio_bl_on: gpio-bl-on {
			fsl,pins = <
				SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04	0x00000021
				SC_P_LVDS1_GPIO00_LSIO_GPIO1_IO10	0x00000021
			>;
		};

		pinctrl_hdmi_lpi2c0: hdmilpi2c0grp {
			fsl,pins = <
				SC_P_HDMI_TX0_TS_SCL_HDMI_TX0_I2C0_SCL  0xc600004c
				SC_P_HDMI_TX0_TS_SDA_HDMI_TX0_I2C0_SDA  0xc600004c
			>;
		};

		pinctrl_hdmi_ctrl: hdmictrlgrp {
			fsl,pins = <
				SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061
			>;
		};

		pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
			fsl,pins = <
				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL	0xc600004c
				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA	0xc600004c
			>;
		};

		pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
			fsl,pins = <
				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL	0xc600004c
				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA	0xc600004c
			>;
		};

		pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
			fsl,pins = <
				SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07		0x00000021
			>;
		};

		/* I2C2 DDC */
		pinctrl_lpi2c0: lpi2c0grp {
			fsl,pins = <
				SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL   0xc600004c
				SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA   0xc600004c
			>;
		};

		pinctrl_lpi2c1: lpi2c1grp {
			fsl,pins = <
				SC_P_GPT0_CLK_DMA_I2C1_SCL              0xc600004c
				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA          0xc600004c
			>;
		};

		pinctrl_lpi2c2: lpi2c2grp {
			fsl,pins = <
				SC_P_GPT1_CLK_DMA_I2C2_SCL              0xc600004c
				SC_P_GPT1_CAPTURE_DMA_I2C2_SDA          0xc600004c
			>;
		};

		pinctrl_lpi2c3: lpi2c3grp {
			fsl,pins = <
				SC_P_SIM0_PD_DMA_I2C3_SCL		0xc600004c
				SC_P_SIM0_POWER_EN_DMA_I2C3_SDA		0xc600004c
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
			>;
		};

		pinctrl_lpuart1: lpuart1grp {
			fsl,pins = <
				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
			>;
		};

		pinctrl_lpuart2: lpuart2grp {
			fsl,pins = <
				SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX	0x06000020
				SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX	0x06000020
			>;
		};

		pinctrl_lpuart3: lpuart3grp {
			fsl,pins = <
				SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX	0x06000020
				SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX	0x06000020
				SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B	0x06000020
				SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B	0x06000020
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				SC_P_ESAI1_TX1_LSIO_GPIO2_IO09		0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
				SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4	0x00000021
				SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5	0x00000021
				SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6	0x00000021
				SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7	0x00000021

				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4	0x00000020
				SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5	0x00000020
				SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6	0x00000020
				SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4	0x00000020
				SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5	0x00000020
				SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6	0x00000020
				SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_flexcan1: flexcan0grp {
			fsl,pins = <
				SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX	0x21
				SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX	0x21
			>;
		};

		pinctrl_flexcan2: flexcan1grp {
			fsl,pins = <
				SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX	0x21
				SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX	0x21
			>;
		};

		pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
			fsl,pins = <
				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27	0x00000021
			>;
		};

		pinctrl_pciea: pcieagrp{
			fsl,pins = <
				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x00000021
				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x00000021
				SC_P_MLB_SIG_LSIO_GPIO3_IO26			0x00000021
			>;
		};

		pinctrl_pcieb: pciebgrp{
			fsl,pins = <
				SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30	0x00000021
				SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31		0x00000021
				SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00		0x00000021
			>;
		};

		pinctrl_sai1: sai1grp {
			fsl,pins = <
				SC_P_SAI1_TXD_AUD_SAI1_TXD		0xc600006c
				SC_P_SAI1_RXC_AUD_SAI1_RXC		0xc600004c
				SC_P_SAI1_TXC_AUD_SAI1_TXC		0xc600004c
				SC_P_SAI1_TXFS_AUD_SAI1_TXFS		0xc600004c
			>;
		};

		pinctrl_usbotg1: usbotg1 {
			fsl,pins = <
				SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR		0x00000021
			>;
		};

		pinctrl_usbh_en: usbhen {
			fsl,pins = <
				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04		0x00000021
			>;
		};

		pinctrl_usb_hsic_idle: usbh1_1 {
			fsl,pins = <
				SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA		0xc60000c5
				SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0xc60000c5
			>;
		};

		pinctrl_usb_hsic_active: usbh1_2 {
			fsl,pins = <
				SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE	0xc60000d5
			>;
		};

		pinctrl_gpio8: gpio8 {
			fsl,pins = <
				SC_P_MLB_DATA_LSIO_GPIO3_IO28			0x00000021
			>;
		};

		pinctrl_usb3503a: usb3503agrp {
			fsl,pins = <
				SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31               0x00000021
				SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01		0x00000021
				SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02               0x00000021
			>;
		};

		pinctrl_wifi: wifigrp {
			fsl,pins = <
				SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28		0x06000021
				SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K	0x06000021
				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24		0x06000021
			>;
		};
	};
};

&gpio2 {
	status = "okay";
};

&gpio5 {
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&usbotg1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg1>;
	srp-disable;
	hnp-disable;
	adp-disable;
	power-polarity-active-high;
	disable-over-current;
	ci-disable-lpm;
	status = "okay";
};

&usbotg3 {
	dr_mode = "host";
	status = "okay";
};

&usbh1 {
	pinctrl-names = "idle", "active";
	pinctrl-0 = <&pinctrl_usb_hsic_idle>;
	pinctrl-1 = <&pinctrl_usb_hsic_active>;
	srp-disable;
	hnp-disable;
	adp-disable;
	disable-over-current;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	fsl,rgmii_txc_dly;
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@7 {
			reg = <7>;
		};
	};
};

&flexcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	/*xceiver-supply = <&reg_can_stby>;*/
	status = "okay";
};

&flexcan2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	/*xceiver-supply = <&reg_can_stby>;*/
	status = "okay";
};

&hdmi {
	compatible = "fsl,imx8qm-hdmi";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_ctrl>;
	hdmi-ctrl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&i2c0_hdmi {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmi_lpi2c0>;
	clock-frequency = <100000>;
	status = "disabled";
};
/*
&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c0>;
	clock-frequency = <100000>;
	status = "okay";
};
*/
&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";

	/* SGTL5000 */
	sgtl5000: codec@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_sgtl5000>;
		reg = <0x0a>;
		clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
		power-domains = <&pd_mclk_out0>;
		assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
				<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
				<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
				<&clk IMX8QM_AUD_MCLKOUT0>;
		assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>;
		VDDA-supply = <&reg_module_3v3_avdd>;
		VDDIO-supply = <&reg_module_3v3>;
		VDDD-supply = <&reg_vref_1v8>;
	};

	/* USB3503A */
	usb3503@08 {
		compatible = "smsc,usb3503a";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb3503a>;
		reg = <0x08>;
		refclk-frequency = <25000000>;
		connect-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
		intn-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
		reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
		initial-mode = <1>;
	};
};

/* Apalis I2C1 */
&i2c2 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c2>;
	status = "okay";

	/* M41T0M6 real time clock on carrier board */
	rtc_i2c: rtc@68 {
		compatible = "st,m41t0";
		reg = <0x68>;
	};
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c3>;
	status = "okay";

	ov5640_mipi@3c {
		compatible = "ovti,ov5640_mipi";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_cam>;
		reg = <0x3c>;
		pwn-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
		rst-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;

		mclk = <24000000>;
		mclk_source = <0>;
		virtual-channel;
		status = "okay";

		port {
			ov5640_ep: endpoint {
				remote-endpoint = <&mipi_csi1_ep>;
				data-lanes = <1 2>;
			};
		};
	};

};

/* Apalis UART3 */
&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

/* Apalis UART1 */
&lpuart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	/* DMA seems not to work when using LPUART as console */
	/delete-property/ dma-names;
	status = "okay";
};

/* Apalis UART4 */
&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "okay";
};

/* Apalis UART2 */
&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "okay";
};

&mipi_csi_1 {
	#address-cells = <1>;
	#size-cells = <0>;
	virtual-channel;
	status = "okay";

	/* Camera 0 MIPI CSI-2 (CSIS1) */
	port@0 {
		reg = <0>;
		mipi_csi1_ep: endpoint {
			remote-endpoint = <&ov5640_ep>;
			data-lanes = <1 2>;
		};
	};
};


&isi_0 {
	status = "okay";
};

&isi_1 {
	status = "okay";
};

&isi_2 {
	status = "okay";
};

&isi_3 {
	status = "okay";
};

&isi_4 {
	status = "okay";
};

&isi_5 {
	status = "okay";
};

&isi_6 {
	status = "okay";
};

&isi_7 {
	status = "okay";
};

&gpu_3d0 {
	status = "okay";
};

&gpu_3d1 {
	status = "okay";
};

&imx8_gpu_ss {
	status = "okay";
};

&prg1 {
	status = "okay";
};

&prg2 {
	status = "okay";
};

&prg3 {
	status = "okay";
};

&prg4 {
	status = "okay";
};

&prg5 {
	status = "okay";
};

&prg6 {
	status = "okay";
};

&prg7 {
	status = "okay";
};

&prg8 {
	status = "okay";
};

&prg9 {
	status = "okay";
};

&dpr1_channel1 {
	status = "okay";
};

&dpr1_channel2 {
	status = "okay";
};

&dpr1_channel3 {
	status = "okay";
};

&dpr2_channel1 {
	status = "okay";
};

&dpr2_channel2 {
	status = "okay";
};

&dpr2_channel3 {
	status = "okay";
};

&dpu1 {
	status = "okay";
};

&prg10 {
	status = "okay";
};

&prg11 {
	status = "okay";
};

&prg12 {
	status = "okay";
};

&prg13 {
	status = "okay";
};

&prg14 {
	status = "okay";
};

&prg15 {
	status = "okay";
};

&prg16 {
	status = "okay";
};

&prg17 {
	status = "okay";
};

&prg18 {
	status = "okay";
};

&dpr3_channel1 {
	status = "okay";
};

&dpr3_channel2 {
	status = "okay";
};

&dpr3_channel3 {
	status = "okay";
};

&dpr4_channel1 {
	status = "okay";
};

&dpr4_channel2 {
	status = "okay";
};

&dpr4_channel3 {
	status = "okay";
};

&dpu2 {
	status = "okay";
};

&pciea{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pciea>;

	ext_osc = <1>;
	clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
		 <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
		 <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
		 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
		 <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>,
		 <&pcie_sata_refclk_gate>;
	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi", "pcie_ext";

	reset-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&pcieb{
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>;

	ext_osc = <1>;
	clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
		 <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
		 <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
		 <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
		 <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>,
		 <&pcie_sata_refclk_gate>;
	clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi", "pcie_ext";

	reset-gpio = <&gpio5 0 GPIO_ACTIVE_HIGH>;
	/*clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>;*/
	/*epdev_on-supply = <&epdev_on>;*/
	status = "okay";
};

&intmux_cm40 {
	status = "okay";
};

&pd_dma_lpuart1 {
       debug_console;
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 * --0xb8000000~0xb800ffff: pingpong
	 */
	vdev-nums = <1>;
	reg = <0x0 0xb8000000 0x0 0x10000>;
	status = "okay";
};

&intmux_cm41 {
	status = "okay";
};

&rpmsg1{
	/*
	 * 64K for one rpmsg instance:
	 * --0xb8100000~0xb810ffff: pingpong
	 */
	vdev-nums = <1>;
	reg = <0x0 0xb8100000 0x0 0x10000>;
	status = "okay";
};

&ldb2_phy {
	status = "disabled";
};

&ldb2 {
	status = "disabled";
	fsl,dual-channel;

	lvds-channel@0 {
		fsl,data-mapping = "spwg";
		fsl,data-width = <18>;
		status = "okay";
		primary;

		display-timings {
			native-mode = <&timing_fullhd>;
			timing_fullhd: 1920x1080 {
				clock-frequency = <138500000>;
				hactive = <1920>;
				vactive = <1080>;
				hback-porch = <80>;
				hfront-porch = <48>;
				vback-porch = <23>;
				vfront-porch = <3>;
				hsync-len = <32>;
				vsync-len = <5>;
				hsync-active = <0>;
				vsync-active = <0>;
				pixelclk-active = <0>;
			};
		};
	};
};

&sai1 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};