1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
|
// SPDX-License-Identifier: GPL-2.0+
// Copyright NXP 2018
#include "fsl-imx8qm-mek-rpmsg.dts"
/ {
sound-cs42888 {
status = "disabled";
};
sound {
status = "disabled";
};
dspaudio: dspaudio {
compatible = "fsl,dsp-audio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>,
<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>,
<&clk IMX8QM_AUD_ASRC_0_IPG>,
<&clk IMX8QM_AUD_ASRC_0_MEM>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
<&clk IMX8QM_ACM_AUD_CLK0_SEL>,
<&clk IMX8QM_ACM_AUD_CLK1_SEL>;
clock-names = "bus", "mclk", "ipg", "mem",
"asrck_0", "asrck_1", "asrck_2", "asrck_3";
assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
power-domains = <&pd_esai0>;
status = "okay";
};
sound-dsp {
compatible = "fsl,imx-dsp-audio";
model = "dsp-audio";
cpu-dai = <&dspaudio>;
audio-codec = <&cs42888>;
audio-platform = <&dsp>;
};
};
&edma2 {
compatible = "fsl,imx8qm-edma";
reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
<0x0 0x59320000 0x0 0x10000>, /* sai4 rx */
<0x0 0x59330000 0x0 0x10000>; /* sai5 tx */
#dma-cells = <3>;
shared-interrupt;
dma-channels = <8>;
interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,/* sai4 */
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;/* sai5 */
interrupt-names = "edma2-chan8-rx", "edma0-chan9-tx", /* spdif0 */
"edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */
"edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */
"edma2-chan18-tx", "edma2-chan19-rx"; /* sai4, sai5 */
pdomains = <&pd_dma2_chan8>, <&pd_dma2_chan9>, /* spdif0 */
<&pd_dma2_chan12>, <&pd_dma2_chan13>, /* sai0 */
<&pd_dma2_chan14>, <&pd_dma2_chan15>, /* sai1 */
<&pd_dma2_chan18>, /* sai4 */
<&pd_dma2_chan19>; /* sai5 */
status = "okay";
};
&dsp {
compatible = "fsl,imx8qm-dsp";
reserved-region = <&dsp_reserved>;
reg = <0x0 0x556e8000 0x0 0x88000>;
clocks = <&clk IMX8QM_AUD_ESAI_0_IPG>,
<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>,
<&clk IMX8QM_AUD_ASRC_0_IPG>,
<&clk IMX8QM_AUD_ASRC_0_MEM>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>,
<&clk IMX8QM_ACM_AUD_CLK0_SEL>,
<&clk IMX8QM_ACM_AUD_CLK1_SEL>;
clock-names = "esai_ipg", "esai_mclk", "asrc_ipg", "asrc_mem",
"asrck_0", "asrck_1", "asrck_2", "asrck_3";
assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
fsl,dsp-firmware = "imx/dsp/hifi4.bin";
fixup-offset = <0x4000000>;
power-domains = <&pd_dsp>;
};
/delete-node/ &pd_dma2_chan0;
/delete-node/ &pd_dma2_chan1;
/delete-node/ &pd_dma2_chan2;
/delete-node/ &pd_dma2_chan3;
/delete-node/ &pd_dma2_chan4;
/delete-node/ &pd_dma2_chan5;
/delete-node/ &pd_dma2_chan6;
/delete-node/ &pd_dma2_chan7;
/delete-node/ &pd_dsp_irqsteer;
/delete-node/ &pd_esai0;
&pd_asrc0 {
reg = <SC_R_ASRC_0>;
power-domains =<&pd_audio_clk1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan0: PD_ASRC_0_RXA {
reg = <SC_R_DMA_2_CH0>;
power-domains =<&pd_asrc0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan1: PD_ASRC_0_RXB {
reg = <SC_R_DMA_2_CH1>;
power-domains =<&pd_dma2_chan0>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan2: PD_ASRC_0_RXC {
reg = <SC_R_DMA_2_CH2>;
power-domains =<&pd_dma2_chan1>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan3: PD_ASRC_0_TXA {
reg = <SC_R_DMA_2_CH3>;
power-domains =<&pd_dma2_chan2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan4: PD_ASRC_0_TXB {
reg = <SC_R_DMA_2_CH4>;
power-domains =<&pd_dma2_chan3>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan5: PD_ASRC_0_TXC {
reg = <SC_R_DMA_2_CH5>;
power-domains =<&pd_dma2_chan4>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan6: PD_ESAI_0_RX {
reg = <SC_R_DMA_2_CH6>;
power-domains =<&pd_dma2_chan5>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan7: PD_ESAI_0_TX {
reg = <SC_R_DMA_2_CH7>;
power-domains =<&pd_dma2_chan6>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_esai0: PD_AUD_ESAI_0 {
reg = <SC_R_ESAI_0>;
power-domains =<&pd_dma2_chan7>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_irqsteer: PD_DSP_IRQSTEER {
reg = <SC_R_IRQSTR_DSP>;
#power-domain-cells = <0>;
power-domains =<&pd_esai0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_mu_A: PD_DSP_MU_A {
reg = <SC_R_MU_13A>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_irqsteer>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_mu_B: PD_DSP_MU_B {
reg = <SC_R_MU_13B>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_mu_A>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp_ram: PD_AUD_OCRAM {
reg = <SC_R_DSP_RAM>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_mu_B>;
#address-cells = <1>;
#size-cells = <0>;
pd_dsp: PD_AUD_DSP {
reg = <SC_R_DSP>;
#power-domain-cells = <0>;
power-domains =<&pd_dsp_ram>;
};
};
};
};
};
};
};
};
};
};
};
};
};
};
};
&esai0 {
status = "disabled";
};
&asrc0 {
status = "disabled";
};
&sai1 {
status = "disabled";
};
&wm8960 {
status = "disabled";
};
&cs42888 {
assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <24576000>, <24576000>;
};
|
