path: root/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts

/*
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

#include "fsl-imx8qm.dtsi"

/ {
	model = "Freescale i.MX8QM MEK";
	compatible = "fsl,imx8qm-mek", "fsl,imx8qm";

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
		stdout-path = &lpuart0;
	};

	modem_reset: modem-reset {
		compatible = "gpio-reset";
		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		epdev_on: fixedregulator@100 {
			compatible = "regulator-fixed";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-name = "epdev_on";
			gpio = <&gpio4 9 0>;
			enable-active-high;
		};

		reg_usdhc2_vmmc: usdhc2_vmmc {
			compatible = "regulator-fixed";
			regulator-name = "sw-3p3-sd1";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};
	};

	sound: sound {
		compatible = "fsl,imx7d-evk-wm8960",
			   "fsl,imx-audio-wm8960";
		model = "wm8960-audio";
		cpu-dai = <&sai1>;
		audio-codec = <&wm8960>;
		asrc-controller = <&asrc0>;
		codec-master;
		/*
		 * hp-det = <hp-det-pin hp-det-polarity>;
		 * hp-det-pin: JD1 JD2  or JD3
		 * hp-det-polarity = 0: hp detect high for headphone
		 * hp-det-polarity = 1: hp detect high for speaker
		 */
		hp-det = <2 0>;
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT2", "Mic Jack",
			"LINPUT3", "Mic Jack",
			"RINPUT1", "Main MIC",
			"RINPUT2", "Main MIC",
			"Mic Jack", "MICB",
			"Main MIC", "MICB",
			"CPU-Playback", "ASRC-Playback",
			"Playback", "CPU-Playback",
			"ASRC-Capture", "CPU-Capture",
			"CPU-Capture", "Capture";
	};

	sound-amix-sai {
		compatible = "fsl,imx-audio-amix";
		model = "amix-audio-sai";
		dais = <&sai6>, <&sai7>;
		amix-controller = <&amix>;
	};
};

&acm {
	status = "okay";
};

&amix {
	status = "okay";
};

&sai6 {
	assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>,
			<&clk IMX8QM_AUD_PLL1_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
			<&clk IMX8QM_AUD_SAI_6_MCLK>;
	assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "okay";
};

&sai7 {
	assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>,
			<&clk IMX8QM_AUD_PLL1_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
			<&clk IMX8QM_AUD_SAI_7_MCLK>;
	assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
	assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
	fsl,sai-asynchronous;
	fsl,txm-rxs;
	status = "okay";
};

&iomuxc {
	imx8qm-mek {
		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000020
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000020
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000020
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000020
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000020
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000020
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000020
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000020
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000020
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000020
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000020
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000020
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL	0x06000020
				SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC	0x06000020
				SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0	0x06000020
				SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1	0x06000020
				SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2	0x06000020
				SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3	0x06000020
				SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC	0x06000020
				SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL	0x06000020
				SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0	0x06000020
				SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1	0x06000020
				SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2	0x06000020
				SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3	0x06000020
			>;
		};

		pinctrl_flexspi0: flexspi0grp {
			fsl,pins = <
				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004c
				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004c
				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004c
				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004c
				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x0600004c
				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004c
				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x0600004c
				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004c
				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004c
				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004c
				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004c
				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004c
				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004c
				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x0600004c
				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004c
				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004c
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				SC_P_UART0_RX_DMA_UART0_RX		0x06000020
				SC_P_UART0_TX_DMA_UART0_TX		0x06000020
			>;
		};

		pinctrl_lpuart1: lpuart1grp {
			fsl,pins = <
				SC_P_UART1_RX_DMA_UART1_RX		0x06000020
				SC_P_UART1_TX_DMA_UART1_TX		0x06000020
				SC_P_UART1_CTS_B_DMA_UART1_CTS_B	0x06000020
				SC_P_UART1_RTS_B_DMA_UART1_RTS_B	0x06000020
				SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22		0x00000021
			>;
		};

		pinctrl_lpuart2: lpuart2grp {
			fsl,pins = <
				SC_P_UART0_RTS_B_DMA_UART2_RX		0x06000020
				SC_P_UART0_CTS_B_DMA_UART2_TX		0x06000020
			>;
		};

		pinctrl_lpuart3: lpuart3grp {
			fsl,pins = <
				SC_P_M41_GPIO0_00_DMA_UART3_RX		0x06000020
				SC_P_M41_GPIO0_01_DMA_UART3_TX		0x06000020
			>;
		};

		pinctrl_mlb: mlbgrp {
			fsl,pins = <
				SC_P_MLB_SIG_CONN_MLB_SIG               0x21
				SC_P_MLB_CLK_CONN_MLB_CLK               0x21
				SC_P_MLB_DATA_CONN_MLB_DATA             0x21
			>;
		};


		pinctrl_sai1: sai1grp {
			fsl,pins = <
				SC_P_SAI1_RXD_AUD_SAI1_RXD		0x0600004c
				SC_P_SAI1_RXC_AUD_SAI1_RXC		0x0600004c
				SC_P_SAI1_RXFS_AUD_SAI1_RXFS		0x0600004c
				SC_P_SAI1_TXD_AUD_SAI1_TXD		0x0600006c
				SC_P_SAI1_TXC_AUD_SAI1_TXC		0x0600004c
				SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0	0x0600004c
			>;
		};

		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				SC_P_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
				SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
			>;
		};

		pinctrl_pciea: pcieagrp{
			fsl,pins = <
				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27	0x00000021
				SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28		0x00000021
				SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29		0x00000021
				SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03		0x00000021
				SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09		0x00000021
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2grpgpio {
			fsl,pins = <
				SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21	0x00000021
				SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22	0x00000021
				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07	0x00000021
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020
			>;
		};
		pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
			fsl,pins = <
				SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL	0xc600004c
				SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA	0xc600004c
			>;
		};

	};
};

&asrc0 {
	fsl,asrc-rate  = <48000>;
	status = "okay";
};

&sai1 {
	assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
			<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
			<&clk IMX8QM_AUD_SAI_1_MCLK>;
	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai1>;
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	bus-width = <4>;
	cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
	vmmc-supply = <&reg_usdhc2_vmmc>;
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	fsl,rgmii_txc_dly;
	fsl,rgmii_rxc_dly;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,eee-disabled;
			at803x,vddio-1p8v;
		};
	};
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt35xu512aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "micron,mt35xu512aba";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <8>;
	};
};

&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	wm8960: wm8960@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
		clock-names = "mclk";
		wlf,shared-lrclk;
		power-domains = <&pd_mclk_out0>;
		assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
				<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
				<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
				<&clk IMX8QM_AUD_MCLKOUT0>;
		assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy1>;
	fsl,magic-packet;
	status = "okay";
};

&lpuart0 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&lpuart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart1>;
	resets = <&modem_reset>;
	status = "okay";
};

&lpuart2 { /* Dbg console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
	status = "disabled";
};

&lpuart3 { /* MKbus */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>;
	status = "okay";
};

&gpu_3d0 {
        status = "okay";
};

&gpu_3d1 {
        status = "okay";
};

&imx8_gpu_ss {
        status = "okay";
};

&dpu1 {
	status = "okay";
};

&dpu2 {
	status = "okay";
};

&pciea{
	ext_osc = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pciea>;
	disable-gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
	reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
	epdev_on-supply = <&epdev_on>;
	status = "okay";
};

&intmux_cm40 {
	status = "okay";
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 * --0xb8000000~0xb800ffff: pingpong
	 */
	vdev-nums = <1>;
	reg = <0x0 0xb8000000 0x0 0x10000>;
	status = "okay";
};

&intmux_cm41 {
	status = "okay";
};

&rpmsg1{
	/*
	 * 64K for one rpmsg instance:
	 * --0xb8100000~0xb810ffff: pingpong
	 */
	vdev-nums = <1>;
	reg = <0x0 0xb8100000 0x0 0x10000>;
	status = "okay";
};

&mipi_csi_0 {
	#address-cells = <1>;
	#size-cells = <0>;
	virtual-channel;
	status = "okay";

	/* Camera 0  MIPI CSI-2 (CSIS0) */
	port@0 {
		reg = <0>;
		mipi_csi0_ep: endpoint {
			remote-endpoint = <&max9286_0_ep>;
			data-lanes = <1 2 3 4>;
		};
	};
};

&mlb {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_mlb>;
	status = "okay";
};

&i2c0_mipi_csi0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	clock-frequency = <100000>;
	status = "okay";

	max9286_mipi@6A	 {
		compatible = "maxim,max9286_mipi";
		reg = <0x6A>;
		clocks = <&clk IMX8QM_CLK_DUMMY>;
		clock-names = "capture_mclk";
		mclk = <27000000>;
		mclk_source = <0>;
		virtual-channel;
		port {
			max9286_0_ep: endpoint {
			remote-endpoint = <&mipi_csi0_ep>;
			data-lanes = <1 2 3 4>;
			};
		};
	};
};

&isi_0 {
	status = "okay";
};

&isi_1 {
	status = "okay";
};

&isi_2 {
	status = "okay";
};

&isi_3 {
	status = "okay";
};

&sata {
	pinctrl-0 = <&pinctrl_pciea>;
	clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&ldb1_phy {
	status = "okay";
};

&ldb1 {
	status = "okay";

	lvds-channel@0 {
		fsl,data-mapping = "jeida";
		fsl,data-width = <24>;
		status = "okay";

		port@1 {
			reg = <1>;

			lvds0_out: endpoint {
				remote-endpoint = <&it6263_0_in>;
			};
		};
	};
};

&i2c1_lvds0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
	clock-frequency = <100000>;
	status = "okay";

	lvds-to-hdmi-bridge@4c {
		compatible = "ite,it6263";
		reg = <0x4c>;

		port {
			it6263_0_in: endpoint {
				clock-lanes = <3>;
				data-lanes = <0 1 2 4>;
				remote-endpoint = <&lvds0_out>;
			};
		};
	};
};