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/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fsl-imx8-ca35.dtsi"
#include <dt-bindings/soc/imx_rsrc.h>
#include <dt-bindings/soc/imx8_hsio.h>
#include <dt-bindings/soc/imx8_pd.h>
#include <dt-bindings/clock/imx8qxp-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>
/ {
model = "Freescale i.MX8QXP MEK";
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
interrupt-parent = <&gic>;
#address-cells = <0x2>;
#size-cells = <0x2>;
aliases {
mmc0 = &usdhc1;
serial2 = &lpuart2;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
enable-method = "psci";
reg = <0x0 0x2>;
/delete-property/ cpu-idle-states;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
enable-method = "psci";
reg = <0x0 0x3>;
/delete-property/ cpu-idle-states;
};
cpu@2 {
/delete-property/ cpu-idle-states;
};
cpu@3 {
/delete-property/ cpu-idle-states;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
clock-frequency = <8333333>;
};
clk: clk {
compatible = "fsl,imx8qxp-clk";
#clock-cells = <1>;
};
iomuxc: iomuxc {
compatible = "fsl,imx8qxp-iomuxc";
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
imx8qx-pm {
#address-cells = <1>;
#size-cells = <0>;
pd_conn: PD_CONN {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_conn_sdch0: PD_CONN_SDHC_0 {
reg = <SC_R_SDHC_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
};
pd_dma: PD_DMA {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma_lpuart2: PD_DMA_UART2 {
reg = <SC_R_UART_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
#address-cells = <1>;
#size-cells = <0>;
/*wakeup-irq = <227>;*/
pd_dma2_chan12: PD_UART2_RX {
reg = <SC_R_DMA_2_CH12>;
power-domains =<&pd_dma_lpuart2>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma2_chan13: PD_UART2_TX {
reg = <SC_R_DMA_2_CH13>;
power-domains =<&pd_dma2_chan12>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
};
mu2: mu@5d1d0000 {
compatible = "fsl,imx8-mu";
reg = <0x0 0x5d1d0000 0x0 0x10000>;
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
fsl,scu_ap_mu_id = <0>;
status = "okay";
};
pci@fd700000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &gic GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
reg = <0x0 0xfd700000 0x0 0x100000>;
ranges = <0x02000000 0x00 0x10000000 0x0 0x10000000 0x00 0x10000>;
};
usdhc1: usdhc@5b010000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x5b010000 0x0 0x10000>;
clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>,
<&clk IMX8QXP_SDHC0_CLK>,
<&clk IMX8QXP_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>;
assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>;
assigned-clock-rates = <0>, <400000000>;
power-domains = <&pd_conn_sdch0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
/* For early console */
lpuart0: serial@5a060000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a060000 0x0 0x1000>;
};
lpuart2: serial@5a080000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a080000 0x0 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
clocks = <&clk IMX8QXP_UART2_CLK>,
<&clk IMX8QXP_UART2_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma2_chan13>;
/*
* dma-names = "tx","rx";
* dmas = <&edma2 13 0 0>,
* <&edma2 12 0 1>;
*/
status = "disabled";
};
};
&iomuxc {
imx8qxp-mek {
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
>;
};
};
};
&lpuart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
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