path: root/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * Copyright 2018-2020 Toradex
 */

#include "dt-bindings/pwm/pwm.h"
#include "imx8qxp.dtsi"

/ {
	model = "Toradex Colibri iMX8QXP/DX Module";
	compatible = "toradex,colibri-imx8x",
		     "fsl,imx8qxp";

	backlight: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */
		status = "disabled";
	};

	chosen {
		bootargs = "console=ttyLP3,115200";
		stdout-path = &lpuart3;
	};

	/* Colibri Parallel RGB */
	display_lcdif: display@disp1 {
                compatible = "fsl,imx-lcdif-mux-display";
                #address-cells = <1>;
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_lcdif>;
                clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>,
                         <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
                clock-names = "bypass_div", "pixel";
                assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>;
                assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>;
                fsl,lcdif-mux-regs = <&lcdif_mux_regs>;
                fsl,interface-pix-fmt = "rgb666";
                power-domains = <&pd IMX_SC_R_LCD_0>;
		status = "disabled";

                port@0 {
                        reg = <0>;

                        lcd_display_in: endpoint {
                                remote-endpoint = <&dpu_disp1_lcdif>;
                        };
                };
        };

	pcie_refclk: pcie-clock-generator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	pcie_refclk_gate: pcie-ref-clock {
		compatible = "gpio-gate-clock";
		#clock-cells = <0>;
		clocks = <&pcie_refclk>;
		enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>;
	};

	reg_module_3v3: regulator-module-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_3v3_avdd: regulator-module-3v3-avdd {
		compatible = "regulator-fixed";
		regulator-name = "+V3.3_AVDD_AUDIO";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_module_vref_1v8: regulator-module-vref-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "vref-1v8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
		 * Shouldn't be used at A core and Linux side.
		 *
		 */
		m4_reserved: m4@0x88000000 {
			no-map;
			reg = <0 0x88000000 0 0x8000000>;
		};

		rpmsg_reserved: rpmsg@0x90000000 {
			no-map;
			reg = <0 0x90200000 0 0x200000>;
		};

		decoder_boot: decoder-boot@84000000 {
			reg = <0 0x84000000 0 0x2000000>;
			no-map;
		};

		encoder_boot: encoder-boot@86000000 {
			reg = <0 0x86000000 0 0x200000>;
			no-map;
		};

		decoder_rpc: decoder-rpc@0x92000000 {
			reg = <0 0x92000000 0 0x200000>;
			no-map;
		};

		encoder_rpc: encoder-rpc@0x92200000 {
			reg = <0 0x92200000 0 0x200000>;
			no-map;
		};

		encoder_reserved: encoder_reserved@94400000 {
			no-map;
			reg = <0 0x94400000 0 0x800000>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0 0x3c000000>;
			alloc-ranges = <0 0x96000000 0 0x3c000000>;
		};

		vdev0vring0: vdev0vring0@90000000 {
			compatible = "shared-dma-pool";
			reg = <0 0x90000000 0 0x8000>;
			no-map;
		};

		vdev0vring1: vdev0vring1@90008000 {
			compatible = "shared-dma-pool";
			reg = <0 0x90008000 0 0x8000>;
			no-map;
		};

		vdev1vring0: vdev1vring0@90010000 {
			compatible = "shared-dma-pool";
			reg = <0 0x90010000 0 0x8000>;
			no-map;
		};

		vdev1vring1: vdev1vring1@90018000 {
			compatible = "shared-dma-pool";
			reg = <0 0x90018000 0 0x8000>;
			no-map;
		};

		vdevbuffer: vdevbuffer {
			compatible = "shared-dma-pool";
			reg = <0 0x90400000 0 0x100000>;
			no-map;
		};
	};

        sound_card: sound-card {
		compatible = "simple-audio-card";
		simple-audio-card,bitclock-master = <&dailink_master>;
		simple-audio-card,format = "i2s";
		simple-audio-card,frame-master = <&dailink_master>;
		simple-audio-card,name = "imx8qxp-sgtl5000";

		dailink_master: simple-audio-card,codec {
			sound-dai = <&sgtl5000_a>;
			clocks = <&mclkout0_lpcg 0>;
		};

		simple-audio-card,cpu {
			sound-dai = <&sai0>;
		};
        };

	vdd_3v3_vga: regulator-vga-avcc {
		compatible = "regulator-fixed";
		regulator-name = "+3.3V_AVCC_VGA";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
        };
};

/* Colibri Analogue Inputs */
&adc0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_adc0>;
	status = "okay";
	vref-supply = <&reg_module_vref_1v8>;
};

/* Colibri PWM_A */
&adma_pwm {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_a>;
	#pwm-cells = <3>;
};

&cameradev {
	status = "disabled";
};

/* Display Prefetch Resolve, (Tiling) */
&dc0_dpr1_channel1 {
	status = "okay";
};

&dc0_dpr1_channel2 {
	status = "okay";
};

&dc0_dpr1_channel3 {
	status = "okay";
};

&dc0_dpr2_channel1 {
	status = "okay";
};

&dc0_dpr2_channel2 {
	status = "okay";
};

&dc0_dpr2_channel3 {
	status = "okay";
};

&dc0_pc {
	status = "okay";
};

&dc0_prg1 {
	status = "okay";
};

&dc0_prg2 {
	status = "okay";
};

&dc0_prg3 {
	status = "okay";
};

&dc0_prg4 {
	status = "okay";
};

&dc0_prg5 {
	status = "okay";
};

&dc0_prg6 {
	status = "okay";
};

&dc0_prg7 {
	status = "okay";
};

&dc0_prg8 {
	status = "okay";
};

&dc0_prg9 {
	status = "okay";
};

&dpu1 {
	status = "okay";
};

&dpu_disp1_lcdif {
	remote-endpoint = <&lcd_display_in>;
};

&enet0_lpcg {
	clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
		 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
		 <&conn_axi_clk>,
		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>,
		 <&conn_ipg_clk>,
		 <&conn_ipg_clk>;
	clock-output-names = "enet0_lpcg_timer_clk",
			     "enet0_lpcg_txc_sampling_clk",
			     "enet0_lpcg_ahb_clk",
			     "enet0_lpcg_ref_50mhz_clk",
			     "enet0_lpcg_ipg_clk",
			     "enet0_lpcg_ipg_s_clk";
};

/* Colibri Ethernet */
&fec1 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&pinctrl_fec1>;
	pinctrl-1 = <&pinctrl_fec1_sleep>;
	phy-mode = "rmii";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	fsl,wakeup_irq = <0>;

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@2 {
			compatible = "ethernet-phy-ieee802.3-c22";
			max-speed = <100>;
			reg = <2>;
		};
	};
};

/* Colibri optional CAN on UART_B RTS/CTS */
&flexcan1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexcan1>;
        xceiver-supply = <&reg_module_3v3>;
};

/* Colibri optional CAN on PS2 */
&flexcan2 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexcan2>;
        xceiver-supply = <&reg_module_3v3>;
};

/* Colibri optional CAN on UART_A TXD/RXD */
&flexcan3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_flexcan3>;
        xceiver-supply = <&reg_module_3v3>;
};

&gpu_3d0 {
	status = "okay";
};

&hsio_refb_clk {
	status = "disabled";
};

/* On-module I2C */
&i2c0 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	/*
	 * There is a shared clock between SGTL5000 and on-module USB hub,
	 * so it is a good way to handle pinmuxing for this clock on a parent
	 * device i2c0
	 */
	pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
	status = "okay";

	/* GPIO expander */
	gpio_expander_43: gpio-expander@43 {
		compatible = "fcs,fxl6408";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x43>;
		inital_io_dir = <0xff>;
		inital_output = <0x05>;
		gpio-line-names = "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_WLAN",
			"PWR_EN_+V3.3_WiFi_N", "PCIe_REF_CLK_EN",
			"USB_RESET_N", "USB_BYPASS_N", "Wi-Fi_PDn",
			"Wi-Fi_WKUP_BT";
	};

	sgtl5000_a: sgtl5000@a {
		compatible = "fsl,sgtl5000";
		#sound-dai-cells = <0>;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				<&mclkout0_lpcg 0>;
		assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>;
		clocks = <&mclkout0_lpcg 0>;
		clock-names = "mclk";
		reg = <0xa>;
		VDDA-supply = <&reg_module_3v3_avdd>;
		VDDIO-supply = <&reg_module_3v3>;
		VDDD-supply = <&reg_module_vref_1v8>;
	};

	/* USB3503A */
	usb3803@8 {
		compatible = "smsc,usb3803";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_usb3503a>;
		assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
				<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
				<&mclkout0_lpcg 0>;
		assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>;
		bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>;
		clocks = <&mclkout0_lpcg 0>;
		clock-names = "refclk";
		disabled-ports = <2>;
		initial-mode = <1>;
		intn-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>;
		non-removable-devices = <1>;
		reg = <0x8>;
		reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>;
	};
};

/* MIPI DSI accessible on FFC (X2) */
&i2c0_mipi_lvds0 {
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
	clock-frequency = <100000>;
};

/* On-module MIPI CSI I2C accessible on FFC (X3) */
&i2c0_mipi_lvds1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
};

/* Colibri I2C */
&i2c1 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
};

&imx8_gpu_ss {
        status = "okay";
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>,
		    <&pinctrl_ext_io0>, <&pinctrl_lpspi2_cs2>;

	colibri-imx8qxp {
		/* Colibri Analogue Inputs */
		pinctrl_adc0: adc0grp {
			fsl,pins = <
				IMX8QXP_ADC_IN0_ADMA_ADC_IN0			0x60		/* SODIMM   8 */
				IMX8QXP_ADC_IN1_ADMA_ADC_IN1			0x60		/* SODIMM   6 */
				IMX8QXP_ADC_IN4_ADMA_ADC_IN4			0x60		/* SODIMM   4 */
				IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60		/* SODIMM   2 */
			>;
		};

		pinctrl_can_int: can-int-grp {
			fsl,pins = <
				IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13		0x40		/* SODIMM  73 */
			>;
		};

		pinctrl_csi_ctl: csictlgrp {
			fsl,pins = <
				IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14		0x20		/* SODIMM  77 */
				IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15		0x20		/* SODIMM  89 */
			>;
		};

		pinctrl_gpiokeys: gpiokeysgrp {
			fsl,pins = <
				IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10		0x06700041	/* SODIMM  45 */
			>;
		};

		/* Colibri UART_B */
		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
				IMX8QXP_UART0_RX_ADMA_UART0_RX			0x06000020	/* SODIMM  36 */
				IMX8QXP_UART0_TX_ADMA_UART0_TX			0x06000020	/* SODIMM  38 */
				IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B		0x06000020	/* SODIMM  34 */
				IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B		0x06000020	/* SODIMM  32 */
			>;
		};

		/* Colibri UART_C */
		pinctrl_lpuart2: lpuart2grp {
			fsl,pins = <
				IMX8QXP_UART2_RX_ADMA_UART2_RX			0x06000020	/* SODIMM  19 */
				IMX8QXP_UART2_TX_ADMA_UART2_TX			0x06000020	/* SODIMM  21 */
			>;
		};

		/* Colibri UART_A */
		pinctrl_lpuart3: lpuart3grp {
			fsl,pins = <
				IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX		0x06000020	/* SODIMM  33 */
				IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX		0x06000020	/* SODIMM  35 */
			>;
		};

		/* Colibri UART_A Control */
		pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
			fsl,pins = <
				IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 	0x20		/* SODIMM  23 */
				IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29		0x20		/* SODIMM  25 */
				IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30		0x20		/* SODIMM  27 */
				IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x20		/* SODIMM  29 */
				IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x20		/* SODIMM  31 */
				IMX8QXP_CSI_EN_LSIO_GPIO3_IO02			0x20		/* SODIMM  37 */
			>;
		};

		/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
		pinctrl_fec1: fec1grp {
			fsl,pins = <
				IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x000014a0 /* Use pads in 3.3V mode */
				IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x000014a0 /* Use pads in 3.3V mode */
				IMX8QXP_ENET0_MDC_CONN_ENET0_MDC		0x06000020
				IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO		0x06000020
				IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
				IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT	0x06000061
				IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61
				IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61
				IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
				IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61
				IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61
				IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER	0x61
			>;
		};

		pinctrl_fec1_sleep: fec1-sleep-grp {
			fsl,pins = <
				IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11		0x06000041
				IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10		0x06000041
				IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x41
				IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29		0x41
				IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31	0x41
				IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x41
				IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04	0x41
				IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05	0x41
				IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06	0x41
				IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07	0x41
			>;
		};

		/* Colibri LCD Back-Light GPIO */
		pinctrl_gpio_bl_on: gpio-bl-on {
			fsl,pins = <
				IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12		0x60		/* SODIMM  71 */
			>;
		};

		pinctrl_hog0: hog0grp {
			fsl,pins = <
				IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0 /* Use pads in 3.3V mode */
			>;
		};

		pinctrl_hog1: hog1grp {
			fsl,pins = <
				IMX8QXP_CSI_D07_CI_PI_D09			0x61		/* SODIMM  65 */
				IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11		0x20		/* SODIMM  69 */
				IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26		0x20		/* SODIMM  79 */
				IMX8QXP_CSI_D02_CI_PI_D04			0x61		/* SODIMM  79 */
				IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03		0x06000020	/* SODIMM  85 */
				IMX8QXP_CSI_D06_CI_PI_D08			0x61		/* SODIMM  85 */
				IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17		0x20		/* SODIMM  95 */
				IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27		0x20		/* SODIMM  97 */
				IMX8QXP_CSI_D03_CI_PI_D05			0x61		/* SODIMM  97 */
				IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18		0x20		/* SODIMM  99 */
				IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28		0x20		/* SODIMM 101 */
				IMX8QXP_CSI_D00_CI_PI_D02			0x61		/* SODIMM 101 */
				IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25		0x20		/* SODIMM 103 */
				IMX8QXP_CSI_D01_CI_PI_D03			0x61		/* SODIMM 103 */
				IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20		/* SODIMM 105 */
				IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05		0x20		/* SODIMM 127 */
				IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06		0x20		/* SODIMM 131 */
				IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04		0x20		/* SODIMM 133 */
				IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x20		/* SODIMM  96 */
				IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20		/* SODIMM  98 */
				IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31		0x20		/* SODIMM 100 */
				IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22		0x20		/* SODIMM 102 */
				IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20		/* SODIMM 104 */
			>;
		};

		pinctrl_hog2: hog2grp {
			fsl,pins = <
				IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x20		/* SODIMM  75 */
				IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x20		/* SODIMM  93 */
			>;
		};

		/*
		 * This pin is used in the SCFW as a UART. Using it from
		 * Linux would require rewritting the SCFW board file.
		 */
		pinctrl_hog_scfw: hogscfwgrp {
			fsl,pins = <
				IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03		0x20		/* SODIMM 144 */
			>;
		};

		/* On Module I2C */
		pinctrl_i2c0: i2c0grp {
			fsl,pins = <
				IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL	0x06000021
				IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA	0x06000021
			>;
		};

		/* Colibri I2C */
		pinctrl_i2c1: i2c1grp {
			fsl,pins = <
				IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL	0x06000021	/* SODIMM 196 */
				IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA	0x06000021	/* SODIMM 194 */
			>;
		};

		/* Colibri optional CAN on UART_B RTS/CTS */
		pinctrl_flexcan1: flexcan0grp {
			fsl,pins = <
				IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX		0x21		/* SODIMM  32 */
				IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX		0x21		/* SODIMM  34 */
			>;
		};

		/* Colibri optional CAN on PS2 */
		pinctrl_flexcan2: flexcan1grp {
			fsl,pins = <
				IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX		0x21		/* SODIMM  55 */
				IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX		0x21		/* SODIMM  63 */
			>;
		};

		/* Colibri optional CAN on UART_A TXD/RXD */
		pinctrl_flexcan3: flexcan2grp {
			fsl,pins = <
				IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX		0x21		/* SODIMM  35 */
				IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX		0x21		/* SODIMM  33 */
			>;
		};

		/* On module wifi module */
		pinctrl_pcieb: pciebgrp {
			fsl,pins = <
				IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x04000061	/* SODIMM 178 */
				IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000061	/* SODIMM  94 */
				IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x60		/* SODIMM  81 */
			>;
		};

		/* Colibri PWM_A */
		pinctrl_pwm_a: pwma {
		/* both pins are connected together, reserve the unused CSI_D05 */
			fsl,pins = <
				IMX8QXP_CSI_D05_CI_PI_D07			0x61		/* SODIMM  59 */
				IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT		0x60		/* SODIMM  59 */
			>;
		};

		/* Colibri PWM_B */
		pinctrl_pwm_b: pwmb {
			fsl,pins = <
				IMX8QXP_UART1_TX_LSIO_PWM0_OUT			0x60		/* SODIMM  28 */
			>;
		};

		/* Colibri PWM_C */
		pinctrl_pwm_c: pwmc {
			fsl,pins = <
				IMX8QXP_UART1_RX_LSIO_PWM1_OUT			0x60		/* SODIMM  30 */
			>;
		};

		/* Colibri PWM_D */
		pinctrl_pwm_d: pwmd {
		/* both pins are connected together, reserve the unused CSI_D04 */
			fsl,pins = <
				IMX8QXP_CSI_D04_CI_PI_D06			0x61		/* SODIMM  67 */
				IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT		0x60		/* SODIMM  67 */
			>;
		};

		/* On-module I2S */
		pinctrl_sai0: sai0grp {
			fsl,pins = <
				IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD			0x06000040
				IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD			0x06000040
				IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC			0x06000040
				IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS			0x06000040
			>;
		};

		/* Colibri Audio Analogue Microphone GND */
		pinctrl_sgtl5000: sgtl5000 {
			fsl,pins = <
				/* MIC GND EN */
				IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06	0x41
			>;
		};

		/* On-module SGTL5000 clock */
		pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk {
			fsl,pins = <
				IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0		0x21
			>;
		};

		/* On-module USB interrupt */
		pinctrl_usb3503a: usb3503a-grp {
			fsl,pins = <
				IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04	0x61
			>;
		};

		/* Colibri USB Client Cable Detect */
		pinctrl_usbc_det: usbc-det {
			fsl,pins = <
				IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09	0x06000040	/* SODIMM 137 */
			>;
		};

		pinctrl_ext_io0: ext-io0 {
			fsl,pins = <
				IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08	0x06000040	/* SODIMM 135 */
			>;
		};

		/* Colibri Parallel RGB LCD Interface */
		pinctrl_lcdif: lcdif-pins {
			fsl,pins = <
				IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19		0x40		/* SODIMM  44 */
				IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN			0x40		/* SODIMM  44 */
				IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK		0x60		/* SODIMM  56 */
				IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC		0x60		/* SODIMM  68 */
				IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC		0x60		/* SODIMM  82 */
				IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00		0x60		/* SODIMM  76 */
				IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x60		/* SODIMM  76 */
				IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01		0x60		/* SODIMM  70 */
				IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02		0x60		/* SODIMM  60 */
				IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03		0x60		/* SODIMM  58 */
				IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04		0x60		/* SODIMM  78 */
				IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05		0x60		/* SODIMM  72 */
				IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06		0x60		/* SODIMM  80 */
				IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07		0x60		/* SODIMM  46 */
				IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08		0x60		/* SODIMM  62 */
				IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09		0x60		/* SODIMM  48 */
				IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10		0x60		/* SODIMM  74 */
				IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11		0x60		/* SODIMM  50 */
				IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12		0x60		/* SODIMM  52 */
				IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13			0x60		/* SODIMM  54 */
				IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14			0x60		/* SODIMM  66 */
				IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15			0x60		/* SODIMM  64 */
				IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16			0x60		/* SODIMM  57 */
				IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x60		/* SODIMM  57 */
				IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17		0x60		/* SODIMM  61 */
			>;
		};

		/* USB Host Power Enable */
		pinctrl_usbh1_reg: usbh1-reg {
			fsl,pins = <
				IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03		0x06000040	/* SODIMM 129 */
			>;
		};

		/* On-module eMMC */
		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
				IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
				IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
				IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
				IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
				IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
				IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
				IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
				IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
				IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
				IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
			>;
		};

		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
				IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
				IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
				IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
				IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
				IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
				IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
				IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
				IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
				IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
				IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
				IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
				IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
				IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD		0x21
				IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
				IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
				IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
				IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
				IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
				IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
				IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
				IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
				IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
				IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x21
			>;
		};

		/* Colibri SDCard CardDetect */
		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
			fsl,pins = <
				IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x06000021	/* SODIMM  43 */
			>;
		};

		pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
			fsl,pins = <
				IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09		0x60		/* SODIMM  43 */
			>;
		};

		/* Colibri SDCard */
		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
				IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
				IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
				IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
				IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
				IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
				IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
				IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
				IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
				IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
				IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
				IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
				IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041	/* SODIMM  47 */
				IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x21		/* SODIMM 190 */
				IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 192 */
				IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM  49 */
				IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM  51 */
				IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM  53 */
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
			>;
		};

		pinctrl_usdhc2_sleep: usdhc2slpgrp {
			fsl,pins = <
				IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23		0x60		/* SODIMM  47 */
				IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24		0x60		/* SODIMM 190 */
				IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 192 */
				IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM  49 */
				IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM  51 */
				IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM  53 */
				IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x21
			>;
		};

		/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
			fsl,pins = <
				IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 	0xc6000020	/* SODIMM 140 */
				IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 	0xc6000020	/* SODIMM 142 */
			>;
		};

		/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
			fsl,pins = <
				IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 	0xc6000020	/* SODIMM 186 */
				IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 	0xc6000020	/* SODIMM 188 */
			>;
		};

		/* Colibri SPI */
		pinctrl_lpspi2: lpspi2 {
			fsl,pins = <
				IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00		0x21		/* SODIMM  86 */
				IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO			0x06000040	/* SODIMM  92 */
				IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI			0x06000040	/* SODIMM  90 */
				IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK			0x06000040	/* SODIMM  88 */
			>;
		};

		pinctrl_lpspi2_cs2: lpspi2-cs2 {
			fsl,pins = <
				IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02	0x21		/* SODIMM  65 */
			>;
		};

		pinctrl_wifi: wifigrp {
			fsl,pins = <
				IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
			>;
		};
	};
};

&isi_0 {
        interface = <2 0 2>;
        /**
         * interface = <Input MIPI_VCx Output>
         * Input:       0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI
         * MIPI_VCx:    0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only
         * Output:      0-DC0, 1-DC1, 2-MEM
         */
};

&isi_1 {
        interface = <6 0 2>;
        parallel_csi;
};

/* Colibri SPI */
&lpspi2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpspi2>;
	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
	status = "okay";

	spidev0: spidev@0 {
		compatible = "toradex,evalspi";
		reg = <0>;
		spi-max-frequency = <10000000>;
	};
};

/* Colibri UART_B */
&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
};

/* Colibri UART_C */
&lpuart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart2>;
};

/* Colibri UART_A */
&lpuart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};

&lsio_gpio0 {
	gpio-line-names = "",
			  "SODIMM_70",
			  "SODIMM_60",
			  "SODIMM_58",
			  "SODIMM_78",
			  "SODIMM_72",
			  "SODIMM_80",
			  "SODIMM_46",
			  "SODIMM_62",
			  "SODIMM_48",
			  "SODIMM_74",
			  "SODIMM_50",
			  "SODIMM_52",
			  "SODIMM_54",
			  "SODIMM_66",
			  "SODIMM_64",
			  "SODIMM_68",
			  "",
			  "",
			  "SODIMM_82",
			  "SODIMM_56",
			  "SODIMM_28",
			  "SODIMM_30",
			  "",
			  "SODIMM_61",
			  "SODIMM_103",
			  "",
			  "",
			  "",
			  "SODIMM_25",
			  "SODIMM_27",
			  "SODIMM_100";
	status = "okay";
};

&lsio_gpio1 {
	gpio-line-names = "SODIMM_86",
			  "SODIMM_92",
			  "SODIMM_90",
			  "SODIMM_88",
			  "",
			  "",
			  "",
			  "SODIMM_59",
			  "",
			  "SODIMM_6",
			  "SODIMM_8",
			  "",
			  "",
			  "SODIMM_2",
			  "SODIMM_4",
			  "SODIMM_34",
			  "SODIMM_32",
			  "SODIMM_63",
			  "SODIMM_55",
			  "SODIMM_33",
			  "SODIMM_35",
			  "SODIMM_36",
			  "SODIMM_38",
			  "SODIMM_21",
			  "SODIMM_19",
			  "SODIMM_140",
			  "SODIMM_142",
			  "SODIMM_196",
			  "SODIMM_194",
			  "SODIMM_186",
			  "SODIMM_188",
			  "SODIMM_138";
	status = "okay";
};

&lsio_gpio2 {
	gpio-line-names = "SODIMM_23",
			  "",
			  "",
			  "SODIMM_144";
	status = "okay";
};

&lsio_gpio3 {
	gpio-line-names = "SODIMM_96",
			  "SODIMM_75",
			  "SODIMM_37",
			  "SODIMM_29",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_43",
			  "SODIMM_45",
			  "SODIMM_69",
			  "SODIMM_71",
			  "SODIMM_73",
			  "SODIMM_77",
			  "SODIMM_89",
			  "SODIMM_93",
			  "SODIMM_95",
			  "SODIMM_99",
			  "SODIMM_105",
			  "SODIMM_107",
			  "SODIMM_98",
			  "SODIMM_102",
			  "SODIMM_104",
			  "SODIMM_106";
	status = "okay";
};

&lsio_gpio4 {
	gpio-line-names = "",
			  "",
			  "",
			  "SODIMM_129",
			  "SODIMM_133",
			  "SODIMM_127",
			  "SODIMM_131",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_44",
			  "",
			  "SODIMM_76",
			  "SODIMM_31",
			  "SODIMM_47",
			  "SODIMM_190",
			  "SODIMM_192",
			  "SODIMM_49",
			  "SODIMM_51",
			  "SODIMM_53";
	status = "okay";
};

&lsio_gpio5 {
	gpio-line-names = "",
			  "SODIMM_57",
			  "SODIMM_65",
			  "SODIMM_85",
			  "",
			  "",
			  "",
			  "",
			  "SODIMM_135",
			  "SODIMM_137",
			  "UNUSABLE_SODIMM_180",
			  "UNUSABLE_SODIMM_184";
	status = "okay";
};

/* MIPI CSI accessible via FFC (X3) */
&mipi_csi_0 {
        #address-cells = <1>;
        #size-cells = <0>;
        /delete-property/virtual-channel;
};

&mipi0_dsi_host {
        pwr-delay = <10>;
};

&mipi1_dsi_host {
        pwr-delay = <10>;
};

/* On-module PCIe for wifi */
&pcieb{
	compatible = "fsl,imx8qxp-pcie","snps,dw-pcie";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>;
	clocks = <&pcieb_lpcg 0>,
		 <&pcieb_lpcg 1>,
		 <&pcieb_lpcg 2>,
		 <&phyx1_lpcg 0>,
		 <&phyx1_crr1_lpcg 0>,
		 <&pcieb_crr3_lpcg 0>,
		 <&misc_crr5_lpcg 0>,
		 <&pcie_refclk_gate>;
		 clock-names = "pcie", "pcie_bus", "pcie_inbound_axi",
		 "pcie_phy", "phy_per", "pcie_per", "misc_per",
		 "pcie_ext";

	clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
	ext_osc = <1>;
	fsl,max-link-speed = <1>;
	hard-wired = <1>;
	disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>;
	power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>;
	reserved-region = <&rpmsg_reserved>;
	reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
	status = "okay";
};

/* Colibri PWM_B */
&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_b>;
	#pwm-cells = <3>;
};

/* Colibri PWM_C */
&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_c>;
	#pwm-cells = <3>;
};

/* Colibri PWM_D */
&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_d>;
	#pwm-cells = <3>;
};

&rpmsg{
	/*
	 * 64K for one rpmsg instance:
	 */
	vdev-nums = <2>;
	reg = <0x0 0x90000000 0x0 0x20000>;
	memory-region = <&vdevbuffer>;
	status = "okay";
};

/* On-module I2S */
&sai0 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai0>;
	status = "okay";
};

&thermal_zones {
	pmic-thermal0 {
		polling-delay-passive = <250>;
		polling-delay = <2000>;
		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;

		trips {
			pmic_alert0: trip0 {
				temperature = <110000>;
				hysteresis = <2000>;
				type = "passive";
			};

			pmic_crit0: trip1 {
				temperature = <125000>;
				hysteresis = <2000>;
				type = "critical";
			};
		};

		cooling-maps {
			map0 {
				trip = <&pmic_alert0>;
				cooling-device =
					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
					<&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
	};
};

/* On-module eMMC */
&usdhc1 {
	bus-width = <8>;
	no-sd;
	no-sdio;
	non-removable;
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	status = "okay";
};

/* Colibri SDCard */
&usdhc2 {
	bus-width = <4>;
	cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
	disable-wp;
	vmmc-supply = <&reg_module_3v3>;
};

&vpu_decoder {
        boot-region = <&decoder_boot>;
        rpc-region = <&decoder_rpc>;
        reg-csr = <0x2d040000>;
        core_type = <1>;
        status = "okay";
};

&vpu_encoder {
        boot-region = <&encoder_boot>;
        rpc-region = <&encoder_rpc>;
        reserved-region = <&encoder_reserved>;
        reg-rpc-system = <0x40000000>;
        resolution-max = <1920 1920>;
        mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx";
        mboxes = <&mu1_m0 0 0
                  &mu1_m0 0 1
                  &mu1_m0 1 0>;
        status = "okay";

        core0@1020000 {
                compatible = "fsl,imx8-mu1-vpu-m0";
                reg = <0x1020000 0x20000>;
                reg-csr = <0x1050000 0x10000>;
                interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
                fsl,vpu_ap_mu_id = <17>;
                fw-buf-size = <0x200000>;
                rpc-buf-size = <0x80000>;
                print-buf-size = <0x80000>;
        };
};