summaryrefslogtreecommitdiff
path: root/arch/unicore32/include/mach/regs-ost.h
blob: 33049a827518a66d657a91d8f144405d5e6ff9a6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
/*
 * PKUnity Operating System Timer (OST) Registers
 */
/*
 * Match Reg 0 OST_OSMR0
 */
#define OST_OSMR0	__REG(PKUNITY_OST_BASE + 0x0000)
/*
 * Match Reg 1 OST_OSMR1
 */
#define OST_OSMR1	__REG(PKUNITY_OST_BASE + 0x0004)
/*
 * Match Reg 2 OST_OSMR2
 */
#define OST_OSMR2	__REG(PKUNITY_OST_BASE + 0x0008)
/*
 * Match Reg 3 OST_OSMR3
 */
#define OST_OSMR3	__REG(PKUNITY_OST_BASE + 0x000C)
/*
 * Counter Reg OST_OSCR
 */
#define OST_OSCR	__REG(PKUNITY_OST_BASE + 0x0010)
/*
 * Status Reg OST_OSSR
 */
#define OST_OSSR	__REG(PKUNITY_OST_BASE + 0x0014)
/*
 * Watchdog Enable Reg OST_OWER
 */
#define OST_OWER	__REG(PKUNITY_OST_BASE + 0x0018)
/*
 * Interrupt Enable Reg OST_OIER
 */
#define OST_OIER	__REG(PKUNITY_OST_BASE + 0x001C)
/*
 * PWM Pulse Width Control Reg OST_PWMPWCR
 */
#define OST_PWMPWCR	__REG(PKUNITY_OST_BASE + 0x0080)
/*
 * PWM Duty Cycle Control Reg OST_PWMDCCR
 */
#define OST_PWMDCCR	__REG(PKUNITY_OST_BASE + 0x0084)
/*
 * PWM Period Control Reg OST_PWMPCR
 */
#define OST_PWMPCR	__REG(PKUNITY_OST_BASE + 0x0088)

/*
 * Match detected 0 OST_OSSR_M0
 */
#define OST_OSSR_M0		FIELD(1, 1, 0)
/*
 * Match detected 1 OST_OSSR_M1
 */
#define OST_OSSR_M1		FIELD(1, 1, 1)
/*
 * Match detected 2 OST_OSSR_M2
 */
#define OST_OSSR_M2		FIELD(1, 1, 2)
/*
 * Match detected 3 OST_OSSR_M3
 */
#define OST_OSSR_M3		FIELD(1, 1, 3)

/*
 * Interrupt enable 0 OST_OIER_E0
 */
#define OST_OIER_E0		FIELD(1, 1, 0)
/*
 * Interrupt enable 1 OST_OIER_E1
 */
#define OST_OIER_E1		FIELD(1, 1, 1)
/*
 * Interrupt enable 2 OST_OIER_E2
 */
#define OST_OIER_E2		FIELD(1, 1, 2)
/*
 * Interrupt enable 3 OST_OIER_E3
 */
#define OST_OIER_E3		FIELD(1, 1, 3)

/*
 * Watchdog Match Enable OST_OWER_WME
 */
#define OST_OWER_WME		FIELD(1, 1, 0)

/*
 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE
 */
#define OST_PWMDCCR_FDCYCLE	FIELD(1, 1, 10)