summaryrefslogtreecommitdiff
path: root/drivers/clk/mvebu/common.h
blob: 783b5631a453fe614e070a51e760e1004d2580e1 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
/*
 * Marvell EBU SoC common clock handling
 *
 * Copyright (C) 2012 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 * Andrew Lunn <andrew@lunn.ch>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2. This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __CLK_MVEBU_COMMON_H_
#define __CLK_MVEBU_COMMON_H_

#include <linux/kernel.h>

extern spinlock_t ctrl_gating_lock;

struct device_node;

struct coreclk_ratio {
	int id;
	const char *name;
};

struct coreclk_soc_desc {
	u32 (*get_tclk_freq)(void __iomem *sar);
	u32 (*get_cpu_freq)(void __iomem *sar);
	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
	bool (*is_sscg_enabled)(void __iomem *sar);
	u32 (*fix_sscg_deviation)(u32 system_clk);
	const struct coreclk_ratio *ratios;
	int num_ratios;
};

struct clk_gating_soc_desc {
	const char *name;
	const char *parent;
	int bit_idx;
	unsigned long flags;
};

void __init mvebu_coreclk_setup(struct device_node *np,
				const struct coreclk_soc_desc *desc);

void __init mvebu_clk_gating_setup(struct device_node *np,
				   const struct clk_gating_soc_desc *desc);

/*
 * This function is shared among the Kirkwood, Armada 370, Armada XP
 * and Armada 375 SoC
 */
u32 kirkwood_fix_sscg_deviation(u32 system_clk);
#endif