diff options
Diffstat (limited to 'recipes-kernel/linux/linux-toradex-rt-3.14.28/0002-ARM-clk-imx6q-fix-video-divider-for-rev-T0-1.0.patch')
| -rw-r--r-- | recipes-kernel/linux/linux-toradex-rt-3.14.28/0002-ARM-clk-imx6q-fix-video-divider-for-rev-T0-1.0.patch | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/recipes-kernel/linux/linux-toradex-rt-3.14.28/0002-ARM-clk-imx6q-fix-video-divider-for-rev-T0-1.0.patch b/recipes-kernel/linux/linux-toradex-rt-3.14.28/0002-ARM-clk-imx6q-fix-video-divider-for-rev-T0-1.0.patch deleted file mode 100644 index d7b852d..0000000 --- a/recipes-kernel/linux/linux-toradex-rt-3.14.28/0002-ARM-clk-imx6q-fix-video-divider-for-rev-T0-1.0.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 5b9eb0cdaefd7ac8e31c1e1812582e0169ba9722 Mon Sep 17 00:00:00 2001 -From: Gary Bisson <bisson.gary@gmail.com> -Date: Wed, 3 Dec 2014 15:03:51 -0800 -Subject: [PATCH 2/3] ARM: clk-imx6q: fix video divider for rev T0 1.0 - -commit 81ef447950bf0955aca46f4a7617d8ce435cf0ce upstream. - -The post dividers do not work on i.MX6Q rev T0 1.0 so they must be fixed -to 1. As the table index was wrong, a divider a of 4 could still be -requested which implied the clock not to be set properly. This is the -root cause of the HDMI not working at high resolution on rev T0 1.0 of -the SoC. - -Signed-off-by: Gary Bisson <bisson.gary@gmail.com> -Cc: <stable@vger.kernel.org> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> - -Upstream-Status: Backport [3.14.29] - ---- - arch/arm/mach-imx/clk-imx6q.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c -index a5107ab..cf060a9 100644 ---- a/arch/arm/mach-imx/clk-imx6q.c -+++ b/arch/arm/mach-imx/clk-imx6q.c -@@ -148,7 +148,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) - post_div_table[1].div = 1; - post_div_table[2].div = 1; - video_div_table[1].div = 1; -- video_div_table[2].div = 1; -+ video_div_table[3].div = 1; - } - - clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); --- -2.1.4 - |