diff options
| author | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-28 15:42:47 +0200 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2018-09-28 16:10:38 +0200 |
| commit | b7459c8f918399ce5378656b7d1261f71c487a02 (patch) | |
| tree | b9a1c468fdbd7b2e78019e2951d646ccf40b5b86 | |
| parent | 868fd11f537b901f0c5eeb36dd03b43d5f527a73 (diff) | |
linux kernel & u-boot recipes: update to latest
Update linux-toradex-mainline to 4.14.72.
While at it drop obsolete linux-toradex-mainline 4.9 recipe.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com>
20 files changed, 7 insertions, 3617 deletions
diff --git a/recipes-bsp/u-boot/u-boot-toradex-fw-utils_git.bb b/recipes-bsp/u-boot/u-boot-toradex-fw-utils_git.bb index 18c1c9c..8113991 100644 --- a/recipes-bsp/u-boot/u-boot-toradex-fw-utils_git.bb +++ b/recipes-bsp/u-boot/u-boot-toradex-fw-utils_git.bb @@ -19,7 +19,7 @@ DEFAULT_PREFERENCE_colibri-t30 = "1" FILESPATHPKG =. "git:" # This revision is based on upstream "v2016.11" -SRCREV = "aca804c9ddadbf34a8ff82779e5598ec5e319f23" +SRCREV = "07edca0bb81857a339f26f3465d5c5602705a94d" SRCBRANCH = "2016.11-toradex" SRCREV_use-head-next = "${AUTOREV}" SRCBRANCH_use-head-next = "2016.11-toradex-next" diff --git a/recipes-bsp/u-boot/u-boot-toradex_git.bb b/recipes-bsp/u-boot/u-boot-toradex_git.bb index 062301a..2ec913d 100644 --- a/recipes-bsp/u-boot/u-boot-toradex_git.bb +++ b/recipes-bsp/u-boot/u-boot-toradex_git.bb @@ -22,7 +22,7 @@ DEFAULT_PREFERENCE_colibri-t30 = "1" FILESPATHPKG =. "git:" S = "${WORKDIR}/git" # This revision is based on upstream "v2016.11" -SRCREV = "aca804c9ddadbf34a8ff82779e5598ec5e319f23" +SRCREV = "07edca0bb81857a339f26f3465d5c5602705a94d" SRCBRANCH = "2016.11-toradex" SRCREV_use-head-next = "${AUTOREV}" SRCBRANCH_use-head-next = "2016.11-toradex-next" diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch deleted file mode 100644 index 86918cb..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch +++ /dev/null @@ -1,2423 +0,0 @@ -From eb5979beac9aaa3be03f1fb3a6542b81f3da2c9f Mon Sep 17 00:00:00 2001 -Message-Id: <eb5979beac9aaa3be03f1fb3a6542b81f3da2c9f.1508244411.git.marcel.ziswiler@toradex.com> -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Mon, 2 Oct 2017 09:27:16 +0200 -Subject: [PATCH] ARM: tegra: apalis-tk1: support v1.2 hardware revision - -Support the V1.2 hardware revision with the following pin muxing -changes: - -Ddc_scl_pv4 and ddc_sda_pv5 previously used as Apalis GPIO3 and GPIO4 -are now used as DDC pins. - -Gen2_i2c_scl_pt5 and gen2_i2c_sda_pt6 previously used as DDC pins are -now used as USB power enable signals. - -Usb_vbus_en0_pn4 and usb_vbus_en1_pn5 previously used as USB power -enable signals are now used as GPIO3 and GPIO4. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts | 299 ++++ - arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 2070 +++++++++++++++++++++++ - 3 files changed, 2370 insertions(+) - create mode 100644 arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts - create mode 100644 arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi - -diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 7037201..1c52eec 100644 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -857,6 +857,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \ - tegra114-tn7.dtb - dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \ - tegra124-apalis-eval.dtb \ -+ tegra124-apalis-v1.2-eval.dtb \ - tegra124-jetson-tk1.dtb \ - tegra124-nyan-big.dtb \ - tegra124-nyan-blaze.dtb \ -diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts -new file mode 100644 -index 0000000..c61eb59 ---- /dev/null -+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts -@@ -0,0 +1,299 @@ -+/* -+ * Copyright 2016-2017 Toradex AG -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+ -+#include <dt-bindings/input/input.h> -+#include "tegra124-apalis-v1.2.dtsi" -+ -+/ { -+ model = "Toradex Apalis TK1 on Apalis Evaluation Board"; -+ compatible = "toradex,apalis-tk1-v1.2-eval", "toradex,apalis-tk1-eval", -+ "toradex,apalis-tk1", "nvidia,tegra124"; -+ -+ aliases { -+ rtc0 = "/i2c@7000c000/rtc@68"; -+ rtc1 = "/i2c@7000d000/pmic@40"; -+ rtc2 = "/rtc@7000e000"; -+ serial0 = &uarta; -+ serial1 = &uartb; -+ serial2 = &uartc; -+ serial3 = &uartd; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ pcie@1003000 { -+ pci@1,0 { -+ status = "okay"; -+ }; -+ }; -+ -+ host1x@50000000 { -+ hdmi@54280000 { -+ status = "okay"; -+ }; -+ }; -+ -+ /* Apalis UART1 */ -+ serial@70006000 { -+ status = "okay"; -+ }; -+ -+ /* Apalis UART2 */ -+ serial@70006040 { -+ status = "okay"; -+ }; -+ -+ /* Apalis UART3 */ -+ serial@70006200 { -+ status = "okay"; -+ }; -+ -+ /* Apalis UART4 */ -+ serial@70006300 { -+ status = "okay"; -+ }; -+ -+ pwm@7000a000 { -+ status = "okay"; -+ }; -+ -+ /* -+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier -+ * board) -+ */ -+ i2c@7000c000 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ -+ pcie-switch@58 { -+ compatible = "plx,pex8605"; -+ reg = <0x58>; -+ }; -+ -+ /* M41T0M6 real time clock on carrier board */ -+ rtc@68 { -+ compatible = "st,m41t00"; -+ reg = <0x68>; -+ }; -+ }; -+ -+ /* GEN2_I2C: unused */ -+ -+ /* -+ * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor -+ * on carrier board) -+ */ -+ i2c@7000c500 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ }; -+ -+ /* -+ * I2C4 (DDC): I2C4_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID) -+ */ -+ hdmi_ddc: i2c@7000c700 { -+ status = "okay"; -+ }; -+ -+ /* SPI1: Apalis SPI1 */ -+ spi@7000d400 { -+ status = "okay"; -+ spi-max-frequency = <50000000>; -+ -+ spidev0: spidev@0 { -+ compatible = "spidev"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+ }; -+ -+ /* SPI4: Apalis SPI2 */ -+ spi@7000da00 { -+ status = "okay"; -+ spi-max-frequency = <50000000>; -+ -+ spidev1: spidev@0 { -+ compatible = "spidev"; -+ reg = <0>; -+ spi-max-frequency = <50000000>; -+ }; -+ }; -+ -+ /* Apalis Serial ATA */ -+ sata@70020000 { -+ status = "okay"; -+ }; -+ -+ hda@70030000 { -+ status = "okay"; -+ }; -+ -+ usb@70090000 { -+ status = "okay"; -+ }; -+ -+ /* Apalis MMC1 */ -+ sdhci@700b0000 { -+ status = "okay"; -+ /* MMC1_CD# */ -+ cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ vqmmc-supply = <&vddio_sdmmc1>; -+ }; -+ -+ /* Apalis SD1 */ -+ sdhci@700b0400 { -+ status = "okay"; -+ /* SD1_CD# */ -+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; -+ bus-width = <4>; -+ vqmmc-supply = <&vddio_sdmmc3>; -+ }; -+ -+ /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ -+ usb@7d000000 { -+ status = "okay"; -+ dr_mode = "otg"; -+ }; -+ -+ usb-phy@7d000000 { -+ status = "okay"; -+ vbus-supply = <®_usbo1_vbus>; -+ }; -+ -+ /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ -+ usb@7d004000 { -+ status = "okay"; -+ }; -+ -+ usb-phy@7d004000 { -+ status = "okay"; -+ vbus-supply = <®_usbh_vbus>; -+ }; -+ -+ /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */ -+ usb@7d008000 { -+ status = "okay"; -+ }; -+ -+ usb-phy@7d008000 { -+ status = "okay"; -+ vbus-supply = <®_usbh_vbus>; -+ }; -+ -+ backlight: backlight { -+ compatible = "pwm-backlight"; -+ /* BKL1_PWM */ -+ pwms = <&pwm 3 5000000>; -+ brightness-levels = <255 231 223 207 191 159 127 0>; -+ default-brightness-level = <6>; -+ /* BKL1_ON */ -+ enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>; -+ }; -+ -+ gpio-keys { -+ compatible = "gpio-keys"; -+ -+ wakeup { -+ label = "WAKE1_MICO"; -+ gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>; -+ linux,code = <KEY_WAKEUP>; -+ debounce-interval = <10>; -+ wakeup-source; -+ }; -+ }; -+ -+ reg_5v0: regulator-5v0 { -+ compatible = "regulator-fixed"; -+ regulator-name = "5V_SW"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ /* USBO1_EN */ -+ reg_usbo1_vbus: regulator-usbo1-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC_USBO1"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_5v0>; -+ }; -+ -+ /* USBH_EN */ -+ reg_usbh_vbus: regulator-usbh-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "VCC_USBH(2A|2C|2D|3|4)"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ gpio = <&gpio TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_5v0>; -+ }; -+}; -+ -+&gpio { -+ lan_reset_n { -+ gpio-hog; -+ gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "LAN_RESET_N"; -+ }; -+ -+ pex_perst_n { -+ gpio-hog; -+ gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "PEX_PERST_N"; -+ }; -+ -+ reset_moci_ctrl { -+ gpio-hog; -+ gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; -+ output-high; -+ line-name = "RESET_MOCI_CTRL"; -+ }; -+}; -diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi -new file mode 100644 -index 0000000..c2b14e69 ---- /dev/null -+++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi -@@ -0,0 +1,2070 @@ -+/* -+ * Copyright 2016-2017 Toradex AG -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This file is distributed in the hope that it will be useful -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "tegra124.dtsi" -+#include "tegra124-apalis-emc.dtsi" -+ -+/* -+ * Toradex Apalis TK1 Module Device Tree -+ * Compatible for Revisions 2GB: V1.2A -+ */ -+/ { -+ model = "Toradex Apalis TK1"; -+ compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1", -+ "nvidia,tegra124"; -+ -+ memory { -+ reg = <0x0 0x80000000 0x0 0x80000000>; -+ }; -+ -+ pcie@1003000 { -+ status = "okay"; -+ avddio-pex-supply = <&vdd_1v05>; -+ avdd-pex-pll-supply = <&vdd_1v05>; -+ avdd-pll-erefe-supply = <&avdd_1v05>; -+ dvddio-pex-supply = <&vdd_1v05>; -+ hvdd-pex-pll-e-supply = <®_3v3>; -+ hvdd-pex-supply = <®_3v3>; -+ vddio-pex-ctl-supply = <®_3v3>; -+ -+ /* Apalis PCIe (additional lane Apalis type specific) */ -+ pci@1,0 { -+ /* PCIE1_RX/TX and TS_DIFF1/2 */ -+ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, -+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; -+ phy-names = "pcie-0", "pcie-1"; -+ }; -+ -+ /* I210 Gigabit Ethernet Controller (On-module) */ -+ pci@2,0 { -+ phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; -+ phy-names = "pcie-0"; -+ status = "okay"; -+ }; -+ }; -+ -+ host1x@50000000 { -+ hdmi@54280000 { -+ pll-supply = <®_1v05_avdd_hdmi_pll>; -+ vdd-supply = <®_3v3_avdd_hdmi>; -+ nvidia,ddc-i2c-bus = <&hdmi_ddc>; -+ nvidia,hpd-gpio = -+ <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ gpu@0,57000000 { -+ /* -+ * Node left disabled on purpose - the bootloader will enable -+ * it after having set the VPR up -+ */ -+ vdd-supply = <&vdd_gpu>; -+ }; -+ -+ pinmux: pinmux@70000868 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&state_default>; -+ -+ state_default: pinmux { -+ /* Analogue Audio (On-module) */ -+ dap3_fs_pp0 { -+ nvidia,pins = "dap3_fs_pp0"; -+ nvidia,function = "i2s2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap3_din_pp1 { -+ nvidia,pins = "dap3_din_pp1"; -+ nvidia,function = "i2s2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ dap3_dout_pp2 { -+ nvidia,pins = "dap3_dout_pp2"; -+ nvidia,function = "i2s2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap3_sclk_pp3 { -+ nvidia,pins = "dap3_sclk_pp3"; -+ nvidia,function = "i2s2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap_mclk1_pw4 { -+ nvidia,pins = "dap_mclk1_pw4"; -+ nvidia,function = "extperiph1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis BKL1_ON */ -+ pbb5 { -+ nvidia,pins = "pbb5"; -+ nvidia,function = "vgp5"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis BKL1_PWM */ -+ pu6 { -+ nvidia,pins = "pu6"; -+ nvidia,function = "pwm3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis CAM1_MCLK */ -+ cam_mclk_pcc0 { -+ nvidia,pins = "cam_mclk_pcc0"; -+ nvidia,function = "vi_alt3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis Digital Audio */ -+ dap2_fs_pa2 { -+ nvidia,pins = "dap2_fs_pa2"; -+ nvidia,function = "hda"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ dap2_sclk_pa3 { -+ nvidia,pins = "dap2_sclk_pa3"; -+ nvidia,function = "hda"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ dap2_din_pa4 { -+ nvidia,pins = "dap2_din_pa4"; -+ nvidia,function = "hda"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ dap2_dout_pa5 { -+ nvidia,pins = "dap2_dout_pa5"; -+ nvidia,function = "hda"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pbb3 { /* DAP1_RESET */ -+ nvidia,pins = "pbb3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ clk3_out_pee0 { -+ nvidia,pins = "clk3_out_pee0"; -+ nvidia,function = "extperiph3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis GPIO */ -+ usb_vbus_en0_pn4 { -+ nvidia,pins = "usb_vbus_en0_pn4"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_DISABLE>; -+ }; -+ usb_vbus_en1_pn5 { -+ nvidia,pins = "usb_vbus_en1_pn5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_DISABLE>; -+ }; -+ pex_l0_rst_n_pdd1 { -+ nvidia,pins = "pex_l0_rst_n_pdd1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ pex_l0_clkreq_n_pdd2 { -+ nvidia,pins = "pex_l0_clkreq_n_pdd2"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ pex_l1_rst_n_pdd5 { -+ nvidia,pins = "pex_l1_rst_n_pdd5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ pex_l1_clkreq_n_pdd6 { -+ nvidia,pins = "pex_l1_clkreq_n_pdd6"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ dp_hpd_pff0 { -+ nvidia,pins = "dp_hpd_pff0"; -+ nvidia,function = "dp"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ pff2 { -+ nvidia,pins = "pff2"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ -+ nvidia,pins = "owr"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis HDMI1_CEC */ -+ hdmi_cec_pee3 { -+ nvidia,pins = "hdmi_cec_pee3"; -+ nvidia,function = "cec"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis HDMI1_HPD */ -+ hdmi_int_pn7 { -+ nvidia,pins = "hdmi_int_pn7"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis I2C1 */ -+ gen1_i2c_scl_pc4 { -+ nvidia,pins = "gen1_i2c_scl_pc4"; -+ nvidia,function = "i2c1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_ENABLE>; -+ }; -+ gen1_i2c_sda_pc5 { -+ nvidia,pins = "gen1_i2c_sda_pc5"; -+ nvidia,function = "i2c1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis I2C3 (CAM) */ -+ cam_i2c_scl_pbb1 { -+ nvidia,pins = "cam_i2c_scl_pbb1"; -+ nvidia,function = "i2c3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_ENABLE>; -+ }; -+ cam_i2c_sda_pbb2 { -+ nvidia,pins = "cam_i2c_sda_pbb2"; -+ nvidia,function = "i2c3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis I2C4 (DDC) */ -+ ddc_scl_pv4 { -+ nvidia,pins = "ddc_scl_pv4"; -+ nvidia,function = "i2c4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; -+ }; -+ ddc_sda_pv5 { -+ nvidia,pins = "ddc_sda_pv5"; -+ nvidia,function = "i2c4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis MMC1 */ -+ sdmmc1_cd_n_pv3 { /* CD# GPIO */ -+ nvidia,pins = "sdmmc1_wp_n_pv3"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ clk2_out_pw5 { /* D5 GPIO */ -+ nvidia,pins = "clk2_out_pw5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc1_dat3_py4 { -+ nvidia,pins = "sdmmc1_dat3_py4"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc1_dat2_py5 { -+ nvidia,pins = "sdmmc1_dat2_py5"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc1_dat1_py6 { -+ nvidia,pins = "sdmmc1_dat1_py6"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc1_dat0_py7 { -+ nvidia,pins = "sdmmc1_dat0_py7"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc1_clk_pz0 { -+ nvidia,pins = "sdmmc1_clk_pz0"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc1_cmd_pz1 { -+ nvidia,pins = "sdmmc1_cmd_pz1"; -+ nvidia,function = "sdmmc1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ clk2_req_pcc5 { /* D4 GPIO */ -+ nvidia,pins = "clk2_req_pcc5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ -+ nvidia,pins = "sdmmc3_clk_lb_in_pee5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ usb_vbus_en2_pff1 { /* D7 GPIO */ -+ nvidia,pins = "usb_vbus_en2_pff1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis PWM */ -+ ph0 { -+ nvidia,pins = "ph0"; -+ nvidia,function = "pwm0"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ph1 { -+ nvidia,pins = "ph1"; -+ nvidia,function = "pwm1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ph2 { -+ nvidia,pins = "ph2"; -+ nvidia,function = "pwm2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ -+ ph3 { -+ nvidia,pins = "ph3"; -+ nvidia,function = "pwm3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis SATA1_ACT# */ -+ dap1_dout_pn2 { -+ nvidia,pins = "dap1_dout_pn2"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis SD1 */ -+ sdmmc3_clk_pa6 { -+ nvidia,pins = "sdmmc3_clk_pa6"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_cmd_pa7 { -+ nvidia,pins = "sdmmc3_cmd_pa7"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_dat3_pb4 { -+ nvidia,pins = "sdmmc3_dat3_pb4"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_dat2_pb5 { -+ nvidia,pins = "sdmmc3_dat2_pb5"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_dat1_pb6 { -+ nvidia,pins = "sdmmc3_dat1_pb6"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_dat0_pb7 { -+ nvidia,pins = "sdmmc3_dat0_pb7"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc3_cd_n_pv2 { /* CD# GPIO */ -+ nvidia,pins = "sdmmc3_cd_n_pv2"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis SPDIF */ -+ spdif_out_pk5 { -+ nvidia,pins = "spdif_out_pk5"; -+ nvidia,function = "spdif"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ spdif_in_pk6 { -+ nvidia,pins = "spdif_in_pk6"; -+ nvidia,function = "spdif"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis SPI1 */ -+ ulpi_clk_py0 { -+ nvidia,pins = "ulpi_clk_py0"; -+ nvidia,function = "spi1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_dir_py1 { -+ nvidia,pins = "ulpi_dir_py1"; -+ nvidia,function = "spi1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ ulpi_nxt_py2 { -+ nvidia,pins = "ulpi_nxt_py2"; -+ nvidia,function = "spi1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_stp_py3 { -+ nvidia,pins = "ulpi_stp_py3"; -+ nvidia,function = "spi1"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis SPI2 */ -+ pg5 { -+ nvidia,pins = "pg5"; -+ nvidia,function = "spi4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg6 { -+ nvidia,pins = "pg6"; -+ nvidia,function = "spi4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg7 { -+ nvidia,pins = "pg7"; -+ nvidia,function = "spi4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ pi3 { -+ nvidia,pins = "pi3"; -+ nvidia,function = "spi4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis UART1 */ -+ pb1 { /* DCD GPIO */ -+ nvidia,pins = "pb1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ pk7 { /* RI GPIO */ -+ nvidia,pins = "pk7"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart1_txd_pu0 { -+ nvidia,pins = "pu0"; -+ nvidia,function = "uarta"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ uart1_rxd_pu1 { -+ nvidia,pins = "pu1"; -+ nvidia,function = "uarta"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart1_cts_n_pu2 { -+ nvidia,pins = "pu2"; -+ nvidia,function = "uarta"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart1_rts_n_pu3 { -+ nvidia,pins = "pu3"; -+ nvidia,function = "uarta"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ uart3_cts_n_pa1 { /* DSR GPIO */ -+ nvidia,pins = "uart3_cts_n_pa1"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart3_rts_n_pc0 { /* DTR GPIO */ -+ nvidia,pins = "uart3_rts_n_pc0"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis UART2 */ -+ uart2_txd_pc2 { -+ nvidia,pins = "uart2_txd_pc2"; -+ nvidia,function = "irda"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ uart2_rxd_pc3 { -+ nvidia,pins = "uart2_rxd_pc3"; -+ nvidia,function = "irda"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart2_cts_n_pj5 { -+ nvidia,pins = "uart2_cts_n_pj5"; -+ nvidia,function = "uartb"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart2_rts_n_pj6 { -+ nvidia,pins = "uart2_rts_n_pj6"; -+ nvidia,function = "uartb"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis UART3 */ -+ uart3_txd_pw6 { -+ nvidia,pins = "uart3_txd_pw6"; -+ nvidia,function = "uartc"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ uart3_rxd_pw7 { -+ nvidia,pins = "uart3_rxd_pw7"; -+ nvidia,function = "uartc"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis UART4 */ -+ uart4_rxd_pb0 { -+ nvidia,pins = "pb0"; -+ nvidia,function = "uartd"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ uart4_txd_pj7 { -+ nvidia,pins = "pj7"; -+ nvidia,function = "uartd"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis USBH_EN */ -+ gen2_i2c_sda_pt6 { -+ nvidia,pins = "gen2_i2c_sda_pt6"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ nvidia,open-drain = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis USBH_OC# */ -+ pbb0 { -+ nvidia,pins = "pbb0"; -+ nvidia,function = "vgp6"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis USBO1_EN */ -+ gen2_i2c_scl_pt5 { -+ nvidia,pins = "gen2_i2c_scl_pt5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ nvidia,open-drain = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Apalis USBO1_OC# */ -+ pbb4 { -+ nvidia,pins = "pbb4"; -+ nvidia,function = "vgp4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* Apalis WAKE1_MICO */ -+ pex_wake_n_pdd3 { -+ nvidia,pins = "pex_wake_n_pdd3"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* CORE_PWR_REQ */ -+ core_pwr_req { -+ nvidia,pins = "core_pwr_req"; -+ nvidia,function = "pwron"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* CPU_PWR_REQ */ -+ cpu_pwr_req { -+ nvidia,pins = "cpu_pwr_req"; -+ nvidia,function = "cpu"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* DVFS */ -+ dvfs_pwm_px0 { -+ nvidia,pins = "dvfs_pwm_px0"; -+ nvidia,function = "cldvfs"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dvfs_clk_px2 { -+ nvidia,pins = "dvfs_clk_px2"; -+ nvidia,function = "cldvfs"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* eMMC */ -+ sdmmc4_dat0_paa0 { -+ nvidia,pins = "sdmmc4_dat0_paa0"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat1_paa1 { -+ nvidia,pins = "sdmmc4_dat1_paa1"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat2_paa2 { -+ nvidia,pins = "sdmmc4_dat2_paa2"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat3_paa3 { -+ nvidia,pins = "sdmmc4_dat3_paa3"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat4_paa4 { -+ nvidia,pins = "sdmmc4_dat4_paa4"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat5_paa5 { -+ nvidia,pins = "sdmmc4_dat5_paa5"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat6_paa6 { -+ nvidia,pins = "sdmmc4_dat6_paa6"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_dat7_paa7 { -+ nvidia,pins = "sdmmc4_dat7_paa7"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_clk_pcc4 { -+ nvidia,pins = "sdmmc4_clk_pcc4"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ sdmmc4_cmd_pt7 { -+ nvidia,pins = "sdmmc4_cmd_pt7"; -+ nvidia,function = "sdmmc4"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* JTAG_RTCK */ -+ jtag_rtck { -+ nvidia,pins = "jtag_rtck"; -+ nvidia,function = "rtck"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* LAN_DEV_OFF# */ -+ ulpi_data5_po6 { -+ nvidia,pins = "ulpi_data5_po6"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* LAN_RESET# */ -+ kb_row10_ps2 { -+ nvidia,pins = "kb_row10_ps2"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* LAN_WAKE# */ -+ ulpi_data4_po5 { -+ nvidia,pins = "ulpi_data4_po5"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* MCU_INT1# */ -+ pk2 { -+ nvidia,pins = "pk2"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* MCU_INT2# */ -+ pj2 { -+ nvidia,pins = "pj2"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* MCU_INT3# */ -+ pi5 { -+ nvidia,pins = "pi5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* MCU_INT4# */ -+ pj0 { -+ nvidia,pins = "pj0"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* MCU_RESET */ -+ pbb6 { -+ nvidia,pins = "pbb6"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* MCU SPI */ -+ gpio_x4_aud_px4 { -+ nvidia,pins = "gpio_x4_aud_px4"; -+ nvidia,function = "spi2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ gpio_x5_aud_px5 { -+ nvidia,pins = "gpio_x5_aud_px5"; -+ nvidia,function = "spi2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ gpio_x6_aud_px6 { /* MCU_CS */ -+ nvidia,pins = "gpio_x6_aud_px6"; -+ nvidia,function = "spi2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ gpio_x7_aud_px7 { -+ nvidia,pins = "gpio_x7_aud_px7"; -+ nvidia,function = "spi2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ gpio_w2_aud_pw2 { /* MCU_CSEZP */ -+ nvidia,pins = "gpio_w2_aud_pw2"; -+ nvidia,function = "spi2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* PMIC_CLK_32K */ -+ clk_32k_in { -+ nvidia,pins = "clk_32k_in"; -+ nvidia,function = "clk"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* PMIC_CPU_OC_INT */ -+ clk_32k_out_pa0 { -+ nvidia,pins = "clk_32k_out_pa0"; -+ nvidia,function = "soc"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* PWR_I2C */ -+ pwr_i2c_scl_pz6 { -+ nvidia,pins = "pwr_i2c_scl_pz6"; -+ nvidia,function = "i2cpwr"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_ENABLE>; -+ }; -+ pwr_i2c_sda_pz7 { -+ nvidia,pins = "pwr_i2c_sda_pz7"; -+ nvidia,function = "i2cpwr"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ nvidia,open-drain = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* PWR_INT_N */ -+ pwr_int_n { -+ nvidia,pins = "pwr_int_n"; -+ nvidia,function = "pmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* RESET_MOCI_CTRL */ -+ pu4 { -+ nvidia,pins = "pu4"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* RESET_OUT_N */ -+ reset_out_n { -+ nvidia,pins = "reset_out_n"; -+ nvidia,function = "reset_out_n"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* SHIFT_CTRL_DIR_IN */ -+ kb_row0_pr0 { -+ nvidia,pins = "kb_row0_pr0"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row1_pr1 { -+ nvidia,pins = "kb_row1_pr1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* Configure level-shifter as output for HDA */ -+ kb_row11_ps3 { -+ nvidia,pins = "kb_row11_ps3"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* SHIFT_CTRL_DIR_OUT */ -+ kb_col5_pq5 { -+ nvidia,pins = "kb_col5_pq5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_col6_pq6 { -+ nvidia,pins = "kb_col6_pq6"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_col7_pq7 { -+ nvidia,pins = "kb_col7_pq7"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* SHIFT_CTRL_OE */ -+ kb_col0_pq0 { -+ nvidia,pins = "kb_col0_pq0"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_col1_pq1 { -+ nvidia,pins = "kb_col1_pq1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_col2_pq2 { -+ nvidia,pins = "kb_col2_pq2"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_col4_pq4 { -+ nvidia,pins = "kb_col4_pq4"; -+ nvidia,function = "kbc"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row2_pr2 { -+ nvidia,pins = "kb_row2_pr2"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ -+ /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ -+ pi6 { -+ nvidia,pins = "pi6"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ /* TOUCH_INT */ -+ gpio_w3_aud_pw3 { -+ nvidia,pins = "gpio_w3_aud_pw3"; -+ nvidia,function = "spi6"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ -+ pc7 { /* NC */ -+ nvidia,pins = "pc7"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg0 { /* NC */ -+ nvidia,pins = "pg0"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg1 { /* NC */ -+ nvidia,pins = "pg1"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg2 { /* NC */ -+ nvidia,pins = "pg2"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg3 { /* NC */ -+ nvidia,pins = "pg3"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pg4 { /* NC */ -+ nvidia,pins = "pg4"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ph4 { /* NC */ -+ nvidia,pins = "ph4"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ph5 { /* NC */ -+ nvidia,pins = "ph5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ph6 { /* NC */ -+ nvidia,pins = "ph6"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ph7 { /* NC */ -+ nvidia,pins = "ph7"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pi0 { /* NC */ -+ nvidia,pins = "pi0"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pi1 { /* NC */ -+ nvidia,pins = "pi1"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pi2 { /* NC */ -+ nvidia,pins = "pi2"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pi4 { /* NC */ -+ nvidia,pins = "pi4"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pi7 { /* NC */ -+ nvidia,pins = "pi7"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pk0 { /* NC */ -+ nvidia,pins = "pk0"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pk1 { /* NC */ -+ nvidia,pins = "pk1"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pk3 { /* NC */ -+ nvidia,pins = "pk3"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pk4 { /* NC */ -+ nvidia,pins = "pk4"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap1_fs_pn0 { /* NC */ -+ nvidia,pins = "dap1_fs_pn0"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap1_din_pn1 { /* NC */ -+ nvidia,pins = "dap1_din_pn1"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap1_sclk_pn3 { /* NC */ -+ nvidia,pins = "dap1_sclk_pn3"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_data7_po0 { /* NC */ -+ nvidia,pins = "ulpi_data7_po0"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_data0_po1 { /* NC */ -+ nvidia,pins = "ulpi_data0_po1"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_data1_po2 { /* NC */ -+ nvidia,pins = "ulpi_data1_po2"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_data2_po3 { /* NC */ -+ nvidia,pins = "ulpi_data2_po3"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_data3_po4 { /* NC */ -+ nvidia,pins = "ulpi_data3_po4"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ ulpi_data6_po7 { /* NC */ -+ nvidia,pins = "ulpi_data6_po7"; -+ nvidia,function = "ulpi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap4_fs_pp4 { /* NC */ -+ nvidia,pins = "dap4_fs_pp4"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap4_din_pp5 { /* NC */ -+ nvidia,pins = "dap4_din_pp5"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap4_dout_pp6 { /* NC */ -+ nvidia,pins = "dap4_dout_pp6"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap4_sclk_pp7 { /* NC */ -+ nvidia,pins = "dap4_sclk_pp7"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_col3_pq3 { /* NC */ -+ nvidia,pins = "kb_col3_pq3"; -+ nvidia,function = "kbc"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row3_pr3 { /* NC */ -+ nvidia,pins = "kb_row3_pr3"; -+ nvidia,function = "kbc"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row4_pr4 { /* NC */ -+ nvidia,pins = "kb_row4_pr4"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row5_pr5 { /* NC */ -+ nvidia,pins = "kb_row5_pr5"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row6_pr6 { /* NC */ -+ nvidia,pins = "kb_row6_pr6"; -+ nvidia,function = "kbc"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row7_pr7 { /* NC */ -+ nvidia,pins = "kb_row7_pr7"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row8_ps0 { /* NC */ -+ nvidia,pins = "kb_row8_ps0"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row9_ps1 { /* NC */ -+ nvidia,pins = "kb_row9_ps1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row12_ps4 { /* NC */ -+ nvidia,pins = "kb_row12_ps4"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row13_ps5 { /* NC */ -+ nvidia,pins = "kb_row13_ps5"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row14_ps6 { /* NC */ -+ nvidia,pins = "kb_row14_ps6"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row15_ps7 { /* NC */ -+ nvidia,pins = "kb_row15_ps7"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row16_pt0 { /* NC */ -+ nvidia,pins = "kb_row16_pt0"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ kb_row17_pt1 { /* NC */ -+ nvidia,pins = "kb_row17_pt1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pu5 { /* NC */ -+ nvidia,pins = "pu5"; -+ nvidia,function = "gmi"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ /* -+ * PCB Version Indication: V1.2 and later have GPIO_PV0 -+ * wired to GND, was NC before -+ */ -+ pv0 { -+ nvidia,pins = "pv0"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pv1 { /* NC */ -+ nvidia,pins = "pv1"; -+ nvidia,function = "rsvd1"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ gpio_x1_aud_px1 { /* NC */ -+ nvidia,pins = "gpio_x1_aud_px1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ gpio_x3_aud_px3 { /* NC */ -+ nvidia,pins = "gpio_x3_aud_px3"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pbb7 { /* NC */ -+ nvidia,pins = "pbb7"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pcc1 { /* NC */ -+ nvidia,pins = "pcc1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ pcc2 { /* NC */ -+ nvidia,pins = "pcc2"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ clk3_req_pee1 { /* NC */ -+ nvidia,pins = "clk3_req_pee1"; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ dap_mclk1_req_pee2 { /* NC */ -+ nvidia,pins = "dap_mclk1_req_pee2"; -+ nvidia,function = "rsvd4"; -+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -+ nvidia,tristate = <TEGRA_PIN_ENABLE>; -+ nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ }; -+ /* -+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output -+ * driver enabled aka not tristated and input driver -+ * enabled as well as it features some magic properties -+ * even though the external loopback is disabled and the -+ * internal loopback used as per -+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 -+ * bits being set to 0xfffd according to the TRM! -+ */ -+ sdmmc3_clk_lb_out_pee4 { /* NC */ -+ nvidia,pins = "sdmmc3_clk_lb_out_pee4"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; -+ }; -+ }; -+ -+ serial@70006040 { -+ compatible = "nvidia,tegra124-hsuart"; -+ }; -+ -+ serial@70006200 { -+ compatible = "nvidia,tegra124-hsuart"; -+ }; -+ -+ serial@70006300 { -+ compatible = "nvidia,tegra124-hsuart"; -+ }; -+ -+ hdmi_ddc: i2c@7000c700 { -+ clock-frequency = <10000>; -+ }; -+ -+ /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ -+ i2c@7000d000 { -+ status = "okay"; -+ clock-frequency = <400000>; -+ -+ /* SGTL5000 audio codec */ -+ sgtl5000: codec@a { -+ compatible = "fsl,sgtl5000"; -+ reg = <0x0a>; -+ VDDA-supply = <®_3v3>; -+ VDDIO-supply = <&vddio_1v8>; -+ clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; -+ }; -+ -+ pmic: pmic@40 { -+ compatible = "ams,as3722"; -+ reg = <0x40>; -+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; -+ ams,system-power-controller; -+ #interrupt-cells = <2>; -+ interrupt-controller; -+ gpio-controller; -+ #gpio-cells = <2>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&as3722_default>; -+ -+ as3722_default: pinmux { -+ gpio2_7 { -+ pins = "gpio2", /* PWR_EN_+V3.3 */ -+ "gpio7"; /* +V1.6_LPO */ -+ function = "gpio"; -+ bias-pull-up; -+ }; -+ -+ gpio0_1_3_4_5_6 { -+ pins = "gpio0", "gpio1", "gpio3", -+ "gpio4", "gpio5", "gpio6"; -+ bias-high-impedance; -+ }; -+ }; -+ -+ regulators { -+ vsup-sd2-supply = <®_3v3>; -+ vsup-sd3-supply = <®_3v3>; -+ vsup-sd4-supply = <®_3v3>; -+ vsup-sd5-supply = <®_3v3>; -+ vin-ldo0-supply = <&vddio_ddr_1v35>; -+ vin-ldo1-6-supply = <®_3v3>; -+ vin-ldo2-5-7-supply = <&vddio_1v8>; -+ vin-ldo3-4-supply = <®_3v3>; -+ vin-ldo9-10-supply = <®_3v3>; -+ vin-ldo11-supply = <®_3v3>; -+ -+ vdd_cpu: sd0 { -+ regulator-name = "+VDD_CPU_AP"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1400000>; -+ regulator-min-microamp = <3500000>; -+ regulator-max-microamp = <3500000>; -+ regulator-always-on; -+ regulator-boot-on; -+ ams,ext-control = <2>; -+ }; -+ -+ sd1 { -+ regulator-name = "+VDD_CORE"; -+ regulator-min-microvolt = <700000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-min-microamp = <2500000>; -+ regulator-max-microamp = <4000000>; -+ regulator-always-on; -+ regulator-boot-on; -+ ams,ext-control = <1>; -+ }; -+ -+ vddio_ddr_1v35: sd2 { -+ regulator-name = -+ "+V1.35_VDDIO_DDR(sd2)"; -+ regulator-min-microvolt = <1350000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ sd3 { -+ regulator-name = -+ "+V1.35_VDDIO_DDR(sd3)"; -+ regulator-min-microvolt = <1350000>; -+ regulator-max-microvolt = <1350000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ vdd_1v05: sd4 { -+ regulator-name = "+V1.05"; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ }; -+ -+ vddio_1v8: sd5 { -+ regulator-name = "+V1.8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ vdd_gpu: sd6 { -+ regulator-name = "+VDD_GPU_AP"; -+ regulator-min-microvolt = <650000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-min-microamp = <3500000>; -+ regulator-max-microamp = <3500000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ avdd_1v05: ldo0 { -+ regulator-name = "+V1.05_AVDD"; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ regulator-boot-on; -+ regulator-always-on; -+ ams,ext-control = <1>; -+ }; -+ -+ vddio_sdmmc1: ldo1 { -+ regulator-name = "VDDIO_SDMMC1"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ ldo2 { -+ regulator-name = "+V1.2"; -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1200000>; -+ regulator-boot-on; -+ regulator-always-on; -+ }; -+ -+ ldo3 { -+ regulator-name = "+V1.05_RTC"; -+ regulator-min-microvolt = <1000000>; -+ regulator-max-microvolt = <1000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ ams,enable-tracking; -+ }; -+ -+ /* 1.8V for LVDS, 3.3V for eDP */ -+ ldo4 { -+ regulator-name = "AVDD_LVDS0_PLL"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ -+ /* LDO5 not used */ -+ -+ vddio_sdmmc3: ldo6 { -+ regulator-name = "VDDIO_SDMMC3"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ /* LDO7 not used */ -+ -+ ldo9 { -+ regulator-name = "+V3.3_ETH(ldo9)"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ ldo10 { -+ regulator-name = "+V3.3_ETH(ldo10)"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ ldo11 { -+ regulator-name = "+V1.8_VPP_FUSE"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ }; -+ }; -+ -+ /* -+ * TMP451 temperature sensor -+ * Note: THERM_N directly connected to AS3722 PMIC THERM -+ */ -+ temperature-sensor@4c { -+ compatible = "ti,tmp451"; -+ reg = <0x4c>; -+ interrupt-parent = <&gpio>; -+ interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; -+ #thermal-sensor-cells = <1>; -+ }; -+ }; -+ -+ /* SPI2: MCU SPI */ -+ spi@7000d600 { -+ status = "okay"; -+ spi-max-frequency = <25000000>; -+ }; -+ -+ pmc@7000e400 { -+ nvidia,invert-interrupt; -+ nvidia,suspend-mode = <1>; -+ nvidia,cpu-pwr-good-time = <500>; -+ nvidia,cpu-pwr-off-time = <300>; -+ nvidia,core-pwr-good-time = <641 3845>; -+ nvidia,core-pwr-off-time = <61036>; -+ nvidia,core-power-req-active-high; -+ nvidia,sys-clock-req-active-high; -+ -+ /* Set power_off bit in ResetControl register of AS3722 PMIC */ -+ i2c-thermtrip { -+ nvidia,i2c-controller-id = <4>; -+ nvidia,bus-addr = <0x40>; -+ nvidia,reg-addr = <0x36>; -+ nvidia,reg-data = <0x2>; -+ }; -+ }; -+ -+ sata@70020000 { -+ phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; -+ phy-names = "sata-0"; -+ avdd-supply = <&vdd_1v05>; -+ hvdd-supply = <®_3v3>; -+ vddio-supply = <&vdd_1v05>; -+ }; -+ -+ usb@70090000 { -+ /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ -+ phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, -+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, -+ <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, -+ <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, -+ <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; -+ phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; -+ avddio-pex-supply = <&vdd_1v05>; -+ avdd-pll-erefe-supply = <&avdd_1v05>; -+ avdd-pll-utmip-supply = <&vddio_1v8>; -+ avdd-usb-ss-pll-supply = <&vdd_1v05>; -+ avdd-usb-supply = <®_3v3>; -+ dvddio-pex-supply = <&vdd_1v05>; -+ hvdd-usb-ss-pll-e-supply = <®_3v3>; -+ hvdd-usb-ss-supply = <®_3v3>; -+ }; -+ -+ padctl@7009f000 { -+ pads { -+ usb2 { -+ status = "okay"; -+ -+ lanes { -+ usb2-0 { -+ nvidia,function = "xusb"; -+ status = "okay"; -+ }; -+ -+ usb2-1 { -+ nvidia,function = "xusb"; -+ status = "okay"; -+ }; -+ -+ usb2-2 { -+ nvidia,function = "xusb"; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ pcie { -+ status = "okay"; -+ -+ lanes { -+ pcie-0 { -+ nvidia,function = "usb3-ss"; -+ status = "okay"; -+ }; -+ -+ pcie-1 { -+ nvidia,function = "usb3-ss"; -+ status = "okay"; -+ }; -+ -+ pcie-2 { -+ nvidia,function = "pcie"; -+ status = "okay"; -+ }; -+ -+ pcie-3 { -+ nvidia,function = "pcie"; -+ status = "okay"; -+ }; -+ -+ pcie-4 { -+ nvidia,function = "pcie"; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ sata { -+ status = "okay"; -+ -+ lanes { -+ sata-0 { -+ nvidia,function = "sata"; -+ status = "okay"; -+ }; -+ }; -+ }; -+ }; -+ -+ ports { -+ /* USBO1 */ -+ usb2-0 { -+ status = "okay"; -+ mode = "otg"; -+ -+ vbus-supply = <®_usbo1_vbus>; -+ }; -+ -+ /* USBH2 */ -+ usb2-1 { -+ status = "okay"; -+ mode = "host"; -+ -+ vbus-supply = <®_usbh_vbus>; -+ }; -+ -+ /* USBH4 */ -+ usb2-2 { -+ status = "okay"; -+ mode = "host"; -+ -+ vbus-supply = <®_usbh_vbus>; -+ }; -+ -+ usb3-0 { -+ nvidia,usb2-companion = <2>; -+ status = "okay"; -+ }; -+ -+ usb3-1 { -+ nvidia,usb2-companion = <0>; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ /* eMMC */ -+ sdhci@700b0600 { -+ status = "okay"; -+ bus-width = <8>; -+ non-removable; -+ }; -+ -+ /* CPU DFLL clock */ -+ clock@70110000 { -+ status = "okay"; -+ vdd-cpu-supply = <&vdd_cpu>; -+ nvidia,i2c-fs-rate = <400000>; -+ }; -+ -+ ahub@70300000 { -+ i2s@70301200 { -+ status = "okay"; -+ }; -+ }; -+ -+ clocks { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ clk32k_in: clock@0 { -+ compatible = "fixed-clock"; -+ reg = <0>; -+ #clock-cells = <0>; -+ clock-frequency = <32768>; -+ }; -+ }; -+ -+ cpus { -+ cpu@0 { -+ vdd-cpu-supply = <&vdd_cpu>; -+ }; -+ }; -+ -+ reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { -+ compatible = "regulator-fixed"; -+ regulator-name = "+V1.05_AVDD_HDMI_PLL"; -+ regulator-min-microvolt = <1050000>; -+ regulator-max-microvolt = <1050000>; -+ gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; -+ vin-supply = <&vdd_1v05>; -+ }; -+ -+ reg_3v3_mxm: regulator-3v3-mxm { -+ compatible = "regulator-fixed"; -+ regulator-name = "+V3.3_MXM"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ }; -+ -+ reg_3v3: regulator-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "+V3.3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ regulator-boot-on; -+ /* PWR_EN_+V3.3 */ -+ gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; -+ enable-active-high; -+ vin-supply = <®_3v3_mxm>; -+ }; -+ -+ reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { -+ compatible = "regulator-fixed"; -+ regulator-name = "+V3.3_AVDD_HDMI"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vdd_1v05>; -+ }; -+ -+ sound { -+ compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", -+ "nvidia,tegra-audio-sgtl5000"; -+ nvidia,model = "Toradex Apalis TK1"; -+ nvidia,audio-routing = -+ "Headphone Jack", "HP_OUT", -+ "LINE_IN", "Line In Jack", -+ "MIC_IN", "Mic Jack"; -+ nvidia,i2s-controller = <&tegra_i2s2>; -+ nvidia,audio-codec = <&sgtl5000>; -+ clocks = <&tegra_car TEGRA124_CLK_PLL_A>, -+ <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, -+ <&tegra_car TEGRA124_CLK_EXTERN1>; -+ clock-names = "pll_a", "pll_a_out0", "mclk"; -+ }; -+ -+ thermal-zones { -+ cpu { -+ trips { -+ cpu-shutdown-trip { -+ temperature = <101000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ mem { -+ trips { -+ mem-shutdown-trip { -+ temperature = <101000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ -+ gpu { -+ trips { -+ gpu-shutdown-trip { -+ temperature = <101000>; -+ hysteresis = <0>; -+ type = "critical"; -+ }; -+ }; -+ }; -+ }; -+}; --- -2.9.5 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-apalis-tk1-remove-spurious-new-lines.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-apalis-tk1-remove-spurious-new-lines.patch deleted file mode 100644 index d6615e9..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-apalis-tk1-remove-spurious-new-lines.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 9986ed08d8135318f19a2f5906427bd816bace93 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Tue, 22 Nov 2016 00:56:25 +0100 -Subject: [RESEND PATCH 1/6] apalis-tk1: remove spurious new lines - -Remove some spurious new lines. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - - arch/arm/boot/dts/tegra124-apalis-eval.dts | 1 - - arch/arm/boot/dts/tegra124-apalis.dtsi | 12 ------------ - 2 files changed, 13 deletions(-) - -diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts -index 653044a..2b5a0f3 100644 ---- a/arch/arm/boot/dts/tegra124-apalis-eval.dts -+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts -@@ -232,7 +232,6 @@ - - backlight: backlight { - compatible = "pwm-backlight"; -- - /* BKL1_PWM */ - pwms = <&pwm 3 5000000>; - brightness-levels = <255 231 223 207 191 159 127 0>; -diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi -index 0819721..6aa4952 100644 ---- a/arch/arm/boot/dts/tegra124-apalis.dtsi -+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi -@@ -56,7 +56,6 @@ - - pcie-controller@01003000 { - status = "okay"; -- - avddio-pex-supply = <&vdd_1v05>; - avdd-pex-pll-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; -@@ -85,7 +84,6 @@ - hdmi@54280000 { - pll-supply = <®_1v05_avdd_hdmi_pll>; - vdd-supply = <®_3v3_avdd_hdmi>; -- - nvidia,ddc-i2c-bus = <&hdmi_ddc>; - nvidia,hpd-gpio = - <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; -@@ -1607,15 +1605,11 @@ - compatible = "ams,as3722"; - reg = <0x40>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; -- - ams,system-power-controller; -- - #interrupt-cells = <2>; - interrupt-controller; -- - gpio-controller; - #gpio-cells = <2>; -- - pinctrl-names = "default"; - pinctrl-0 = <&as3722_default>; - -@@ -1790,7 +1784,6 @@ - reg = <0x4c>; - interrupt-parent = <&gpio>; - interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; -- - #thermal-sensor-cells = <1>; - }; - }; -@@ -1823,7 +1816,6 @@ - sata@70020000 { - phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; - phy-names = "sata-0"; -- - avdd-supply = <&vdd_1v05>; - hvdd-supply = <®_3v3>; - vddio-supply = <&vdd_1v05>; -@@ -1837,7 +1829,6 @@ - <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, - <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; - phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; -- - avddio-pex-supply = <&vdd_1v05>; - avdd-pll-erefe-supply = <&avdd_1v05>; - avdd-pll-utmip-supply = <&vddio_1v8>; -@@ -1919,7 +1910,6 @@ - usb2-0 { - status = "okay"; - mode = "otg"; -- - vbus-supply = <®_usbo1_vbus>; - }; - -@@ -1927,7 +1917,6 @@ - usb2-1 { - status = "okay"; - mode = "host"; -- - vbus-supply = <®_usbh_vbus>; - }; - -@@ -1935,7 +1924,6 @@ - usb2-2 { - status = "okay"; - mode = "host"; -- - vbus-supply = <®_usbh_vbus>; - }; - --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch deleted file mode 100644 index c958ff6..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch +++ /dev/null @@ -1,147 +0,0 @@ -From a2286569bb02b2ef881302eedbd944f8482beabe Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Thu, 15 Dec 2016 10:24:58 +0100 -Subject: [PATCH 1/4] apalis_t30/tk1: fix pcie clock and reset not conforming - to specification - -Fix PCIe clock and reset not conforming to specification by moving PCIe -reset handling including the PLX PEX 8605 errata 5 workaround from the -board platform data into the right places timing wise in the PCIe driver -itself. - -Also add a kernel command line argument to allow using the Apalis GPIO7 -as a regular GPIO rather than for above mentioned PLX PEX 8605 -workaround: - -pex_perst=0 - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> -(cherry picked from toradex_tk1_l4t_r21.5 commit -3e2259b04c2e2c029f742e9dda06a3a2739977d4) -(cherry picked from tegra commit -a2f63805703b43d55d91ae17f10d0049bf0f625e) - ---- - - drivers/pci/host/pci-tegra.c | 83 ++++++++++++++++++++++++++++++++++++++++++++ - 1 file changed, 83 insertions(+) - -diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c -index 8dfccf7..1452fe4 100644 ---- a/drivers/pci/host/pci-tegra.c -+++ b/drivers/pci/host/pci-tegra.c -@@ -55,6 +55,34 @@ - #include <asm/mach/map.h> - #include <asm/mach/pci.h> - -+//#define CONFIG_MACH_APALIS_T30 -+#define CONFIG_MACH_APALIS_TK1 -+#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) -+#include <linux/gpio.h> -+ -+#include "../../../arch/arm/boot/dts/include/dt-bindings/gpio/tegra-gpio.h" -+ -+#ifdef CONFIG_MACH_APALIS_T30 -+#define APALIS_GPIO7 TEGRA_GPIO(S, 7) -+ -+#define LAN_RESET_N -1 -+ -+#define PEX_PERST_N APALIS_GPIO7 -+ -+#define RESET_MOCI_N TEGRA_GPIO(I, 4) -+#endif -+ -+#ifdef CONFIG_MACH_APALIS_TK1 -+#define APALIS_GPIO7 TEGRA_GPIO(DD, 1) -+ -+#define LAN_RESET_N TEGRA_GPIO(S, 2) -+ -+#define PEX_PERST_N APALIS_GPIO7 -+ -+#define RESET_MOCI_N TEGRA_GPIO(U, 4) -+#endif -+#endif -+ - #define INT_PCI_MSI_NR (8 * 32) - - /* register definitions */ -@@ -322,6 +350,21 @@ struct tegra_pcie_bus { - unsigned int nr; - }; - -+#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) -+/* To disable the PCIe switch reset errata workaround */ -+int g_pex_perst = 1; -+ -+/* To disable the PCIe switch reset errata workaround */ -+static int __init disable_pex_perst(char *s) -+{ -+ if (!(*s) || !strcmp(s, "0")) -+ g_pex_perst = 0; -+ -+ return 0; -+} -+__setup("pex_perst=", disable_pex_perst); -+#endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ -+ - static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys) - { - return sys->private_data; -@@ -528,6 +571,27 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) - unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port); - unsigned long value; - -+#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) -+ /* -+ * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation -+ * Board -+ */ -+ if (g_pex_perst) -+ gpio_request(PEX_PERST_N, "PEX_PERST_N"); -+ gpio_request(RESET_MOCI_N, "RESET_MOCI_N"); -+ if (g_pex_perst) -+ gpio_direction_output(PEX_PERST_N, 0); -+ gpio_direction_output(RESET_MOCI_N, 0); -+ -+#ifdef CONFIG_MACH_APALIS_TK1 -+ /* Reset I210 Gigabit Ethernet Controller */ -+ if (LAN_RESET_N) { -+ gpio_request(LAN_RESET_N, "LAN_RESET_N"); -+ gpio_direction_output(LAN_RESET_N, 0); -+ } -+#endif /* CONFIG_MACH_APALIS_TK1 */ -+#endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ -+ - /* pulse reset signal */ - value = afi_readl(port->pcie, ctrl); - value &= ~AFI_PEX_CTRL_RST; -@@ -538,6 +602,25 @@ static void tegra_pcie_port_reset(struct tegra_pcie_port *port) - value = afi_readl(port->pcie, ctrl); - value |= AFI_PEX_CTRL_RST; - afi_writel(port->pcie, value, ctrl); -+ -+#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_APALIS_TK1) -+ /* Must be asserted for 100 ms after power and clocks are stable */ -+ if (g_pex_perst) -+ gpio_set_value(PEX_PERST_N, 1); -+ /* -+ * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until -+ * 900 us After PEX_PERST# De-assertion -+ */ -+ if (g_pex_perst) -+ mdelay(1); -+ gpio_set_value(RESET_MOCI_N, 1); -+ -+#ifdef CONFIG_MACH_APALIS_TK1 -+ /* Release I210 Gigabit Ethernet Controller Reset */ -+ if (LAN_RESET_N) -+ gpio_set_value(LAN_RESET_N, 1); -+#endif /* CONFIG_MACH_APALIS_TK1 */ -+#endif /* CONFIG_MACH_APALIS_T30 || CONFIG_MACH_APALIS_TK1 */ - } - - static void tegra_pcie_port_enable(struct tegra_pcie_port *port) --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch deleted file mode 100644 index 48a560b..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-drm-tegra-add-tiling-FB-modifiers.patch +++ /dev/null @@ -1,128 +0,0 @@ -From 779ca8b35effc59faeeb24ed20a61f95035928fd Mon Sep 17 00:00:00 2001 -From: Alexandre Courbot <acourbot@nvidia.com> -Date: Fri, 16 Sep 2016 23:46:31 +0900 -Subject: [PATCH] drm/tegra: add tiling FB modifiers - -Add FB modifiers to allow user-space to specify that a surface is in one -of the two tiling formats supported by Tegra chips, and add support in -the tegradrm driver to handle them properly. This is necessary for the -display controller to directly display buffers generated by the GPU. - -This feature is intended to replace the dedicated IOCTL enabled -by TEGRA_STAGING and to provide a non-staging alternative to that -solution. - -Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> -Acked-by: Daniel Vetter <daniel@ffwll.ch> ---- - drivers/gpu/drm/tegra/drm.c | 2 ++ - drivers/gpu/drm/tegra/fb.c | 23 +++++++++++++++++++--- - include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++ - 3 files changed, 67 insertions(+), 3 deletions(-) - -diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c -index b8be3ee..13a1524 100644 ---- a/drivers/gpu/drm/tegra/drm.c -+++ b/drivers/gpu/drm/tegra/drm.c -@@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) - drm->mode_config.max_width = 4096; - drm->mode_config.max_height = 4096; - -+ drm->mode_config.allow_fb_modifiers = true; -+ - drm->mode_config.funcs = &tegra_drm_mode_funcs; - - err = tegra_drm_fb_prepare(drm); -diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c -index e4a5ab0..3faf38a 100644 ---- a/drivers/gpu/drm/tegra/fb.c -+++ b/drivers/gpu/drm/tegra/fb.c -@@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer, - struct tegra_bo_tiling *tiling) - { - struct tegra_fb *fb = to_tegra_fb(framebuffer); -- -- /* TODO: handle YUV formats? */ -- *tiling = fb->planes[0]->tiling; -+ uint64_t modifier = fb->base.modifier; -+ -+ switch (fourcc_mod_tegra_mod(modifier)) { -+ case NV_FORMAT_MOD_TEGRA_TILED: -+ tiling->mode = TEGRA_BO_TILING_MODE_TILED; -+ tiling->value = 0; -+ break; -+ -+ case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0): -+ tiling->mode = TEGRA_BO_TILING_MODE_BLOCK; -+ tiling->value = fourcc_mod_tegra_param(modifier); -+ if (tiling->value > 5) -+ return -EINVAL; -+ break; -+ -+ default: -+ /* TODO: handle YUV formats? */ -+ *tiling = fb->planes[0]->tiling; -+ break; -+ } - - return 0; - } -diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h -index a5890bf..967dfab 100644 ---- a/include/uapi/drm/drm_fourcc.h -+++ b/include/uapi/drm/drm_fourcc.h -@@ -233,6 +233,51 @@ extern "C" { - */ - #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1) - -+ -+/* NVIDIA Tegra frame buffer modifiers */ -+ -+/* -+ * Some modifiers take parameters, for example the number of vertical GOBs in -+ * a block. Reserve the lower 32 bits for parameters -+ */ -+#define __fourcc_mod_tegra_mode_shift 32 -+#define fourcc_mod_tegra_code(val, params) \ -+ fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params)) -+#define fourcc_mod_tegra_mod(m) \ -+ (m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -+#define fourcc_mod_tegra_param(m) \ -+ (m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1)) -+ -+/* -+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4. -+ * -+ * Pixels are arranged in simple tiles of 16 x 16 bytes. -+ */ -+#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0) -+ -+/* -+ * Tegra 16Bx2 Block Linear layout, used by TK1/TX1 -+ * -+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked -+ * vertically by a power of 2 (1 to 32 GOBs) to form a block. -+ * -+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape. -+ * -+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically. -+ * Valid values are: -+ * -+ * 0 == ONE_GOB -+ * 1 == TWO_GOBS -+ * 2 == FOUR_GOBS -+ * 3 == EIGHT_GOBS -+ * 4 == SIXTEEN_GOBS -+ * 5 == THIRTYTWO_GOBS -+ * -+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format -+ * in full detail. -+ */ -+#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v) -+ - #if defined(__cplusplus) - } - #endif --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-tegra_defconfig-snapd-squashfs-configuration.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-tegra_defconfig-snapd-squashfs-configuration.patch deleted file mode 100644 index 19ed5c3..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-tegra_defconfig-snapd-squashfs-configuration.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 1768b153330d09acc3e98d53d5aa2c4519a68588 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Sun, 18 Jun 2017 01:23:26 +0200 -Subject: [PATCH] tegra_defconfig: snapd squashfs configuration - -Prepare for snapd integration. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - arch/arm/configs/tegra_defconfig | 9 ++++++++- - 1 files changed, 8 insertions(+), 1 deletions(-) - -diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig -index cc9a4c4..a63dbf7 100644 ---- a/arch/arm/configs/tegra_defconfig -+++ b/arch/arm/configs/tegra_defconfig -@@ -278,7 +278,12 @@ CONFIG_EXT3_FS_SECURITY=y - CONFIG_VFAT_FS=y - CONFIG_TMPFS=y - CONFIG_TMPFS_POSIX_ACL=y --CONFIG_SQUASHFS=y -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_FILE_DIRECT=y -+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_ZLIB=y -+CONFIG_SQUASHFS_LZ4=y - CONFIG_SQUASHFS_LZO=y - CONFIG_SQUASHFS_XZ=y - CONFIG_NFS_FS=y --- -2.9.4 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-toradex_apalis_tk1_t30-customize-defconfig.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-toradex_apalis_tk1_t30-customize-defconfig.patch deleted file mode 100644 index 6f1a010..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0001-toradex_apalis_tk1_t30-customize-defconfig.patch +++ /dev/null @@ -1,181 +0,0 @@ -From dbb1d8b04577f892dbaa0a5d086a0ec2c08dc00f Mon Sep 17 00:00:00 2001 -From: Dominik Sliwa <dominik.sliwa@toradex.com> -Date: Thu, 15 Dec 2016 10:40:06 +0100 -Subject: [PATCH] toradex_apalis_tk1_t30: customize defconfig - ---- - arch/arm/configs/tegra_defconfig | 45 ++++++++++++++++++++++++---------------- - 1 file changed, 27 insertions(+), 18 deletions(-) - -diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig -index 6012a1e..48f87cd 100644 ---- a/arch/arm/configs/tegra_defconfig -+++ b/arch/arm/configs/tegra_defconfig -@@ -1,16 +1,15 @@ - CONFIG_SYSVIPC=y --CONFIG_FHANDLE=y - CONFIG_IRQ_DOMAIN_DEBUG=y - CONFIG_NO_HZ=y - CONFIG_HIGH_RES_TIMERS=y - CONFIG_IKCONFIG=y - CONFIG_IKCONFIG_PROC=y - CONFIG_CGROUPS=y --CONFIG_CGROUP_DEBUG=y --CONFIG_CGROUP_FREEZER=y --CONFIG_CGROUP_CPUACCT=y - CONFIG_CGROUP_SCHED=y - CONFIG_RT_GROUP_SCHED=y -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_DEBUG=y - CONFIG_BLK_DEV_INITRD=y - # CONFIG_ELF_CORE is not set - CONFIG_EMBEDDED=y -@@ -24,14 +23,10 @@ CONFIG_PARTITION_ADVANCED=y - # CONFIG_IOSCHED_DEADLINE is not set - # CONFIG_IOSCHED_CFQ is not set - CONFIG_ARCH_TEGRA=y --CONFIG_ARCH_TEGRA_2x_SOC=y --CONFIG_ARCH_TEGRA_3x_SOC=y --CONFIG_ARCH_TEGRA_114_SOC=y --CONFIG_ARCH_TEGRA_124_SOC=y - CONFIG_PCI=y -+CONFIG_PCIEPORTBUS=y - CONFIG_PCI_MSI=y - CONFIG_PCI_TEGRA=y --CONFIG_PCIEPORTBUS=y - CONFIG_SMP=y - CONFIG_PREEMPT=y - CONFIG_AEABI=y -@@ -41,7 +36,6 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 - CONFIG_ZBOOT_ROM_BSS=0x0 - CONFIG_KEXEC=y - CONFIG_CPU_FREQ=y --CONFIG_CPU_FREQ_STAT_DETAILS=y - CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y - CONFIG_CPUFREQ_DT=y - CONFIG_CPU_IDLE=y -@@ -59,7 +53,6 @@ CONFIG_IP_PNP_RARP=y - CONFIG_INET_ESP=y - # CONFIG_INET_XFRM_MODE_TUNNEL is not set - # CONFIG_INET_XFRM_MODE_BEET is not set --# CONFIG_INET_LRO is not set - # CONFIG_INET_DIAG is not set - CONFIG_IPV6_ROUTER_PREF=y - CONFIG_IPV6_OPTIMISTIC_DAD=y -@@ -110,9 +103,21 @@ CONFIG_USB_PEGASUS=y - CONFIG_USB_USBNET=y - CONFIG_USB_NET_SMSC75XX=y - CONFIG_USB_NET_SMSC95XX=y -+CONFIG_ATH9K=m -+CONFIG_ATH9K_CHANNEL_CONTEXT=y -+CONFIG_ATH9K_HTC=m -+CONFIG_ATH10K=m -+CONFIG_ATH10K_PCI=m -+# CONFIG_WLAN_VENDOR_ATMEL is not set - CONFIG_BRCMFMAC=m -+CONFIG_IWLWIFI=m -+CONFIG_IWLDVM=m -+CONFIG_IWLMVM=m - CONFIG_RT2X00=y - CONFIG_RT2800USB=m -+CONFIG_RTL_CARDS=m -+CONFIG_RTL8192CU=m -+CONFIG_RSI_91X=m - CONFIG_INPUT_JOYDEV=y - CONFIG_INPUT_EVDEV=y - CONFIG_KEYBOARD_GPIO=y -@@ -131,8 +136,8 @@ CONFIG_INPUT_MPU3050=y - # CONFIG_DEVKMEM is not set - CONFIG_SERIAL_8250=y - CONFIG_SERIAL_8250_CONSOLE=y --CONFIG_SERIAL_TEGRA=y - CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_TEGRA=y - # CONFIG_HW_RANDOM is not set - # CONFIG_I2C_COMPAT is not set - CONFIG_I2C_CHARDEV=y -@@ -151,11 +156,11 @@ CONFIG_GPIO_PCA953X_IRQ=y - CONFIG_GPIO_PALMAS=y - CONFIG_GPIO_TPS6586X=y - CONFIG_GPIO_TPS65910=y --CONFIG_BATTERY_SBS=y --CONFIG_CHARGER_TPS65090=y - CONFIG_POWER_RESET=y - CONFIG_POWER_RESET_AS3722=y - CONFIG_POWER_RESET_GPIO=y -+CONFIG_BATTERY_SBS=y -+CONFIG_CHARGER_TPS65090=y - CONFIG_SENSORS_LM90=y - CONFIG_SENSORS_LM95245=y - CONFIG_WATCHDOG=y -@@ -188,6 +193,7 @@ CONFIG_USB_GSPCA=y - CONFIG_DRM=y - CONFIG_DRM_NOUVEAU=m - CONFIG_DRM_TEGRA=y -+CONFIG_DRM_TEGRA_STAGING=y - CONFIG_DRM_PANEL_SIMPLE=y - # CONFIG_LCD_CLASS_DEVICE is not set - # CONFIG_BACKLIGHT_GENERIC is not set -@@ -216,9 +222,10 @@ CONFIG_SND_SOC_TEGRA_WM9712=y - CONFIG_SND_SOC_TEGRA_TRIMSLICE=y - CONFIG_SND_SOC_TEGRA_ALC5632=y - CONFIG_SND_SOC_TEGRA_MAX98090=y -+CONFIG_SND_SOC_TEGRA_SGTL5000=y - CONFIG_USB=y - CONFIG_USB_XHCI_HCD=y --CONFIG_USB_XHCI_TEGRA=y -+CONFIG_USB_XHCI_TEGRA=m - CONFIG_USB_EHCI_HCD=y - CONFIG_USB_EHCI_TEGRA=y - CONFIG_USB_ACM=y -@@ -229,11 +236,9 @@ CONFIG_MMC_BLOCK_MINORS=16 - CONFIG_MMC_SDHCI=y - CONFIG_MMC_SDHCI_PLTFM=y - CONFIG_MMC_SDHCI_TEGRA=y --CONFIG_NEW_LEDS=y - CONFIG_LEDS_CLASS=y - CONFIG_LEDS_GPIO=y - CONFIG_LEDS_PWM=y --CONFIG_LEDS_TRIGGERS=y - CONFIG_LEDS_TRIGGER_TIMER=y - CONFIG_LEDS_TRIGGER_ONESHOT=y - CONFIG_LEDS_TRIGGER_HEARTBEAT=y -@@ -253,6 +258,7 @@ CONFIG_RTC_DRV_TEGRA=y - CONFIG_DMADEVICES=y - CONFIG_TEGRA20_APB_DMA=y - CONFIG_STAGING=y -+CONFIG_R8188EU=m - CONFIG_SENSORS_ISL29018=y - CONFIG_SENSORS_ISL29028=y - CONFIG_MFD_NVEC=y -@@ -262,6 +268,10 @@ CONFIG_NVEC_POWER=y - CONFIG_NVEC_PAZ00=y - CONFIG_TEGRA_IOMMU_GART=y - CONFIG_TEGRA_IOMMU_SMMU=y -+CONFIG_ARCH_TEGRA_2x_SOC=y -+CONFIG_ARCH_TEGRA_3x_SOC=y -+CONFIG_ARCH_TEGRA_114_SOC=y -+CONFIG_ARCH_TEGRA_124_SOC=y - CONFIG_MEMORY=y - CONFIG_IIO=y - CONFIG_AK8975=y -@@ -286,6 +286,7 @@ CONFIG_EXT3_FS=y - CONFIG_EXT3_FS_POSIX_ACL=y - CONFIG_EXT3_FS_SECURITY=y - # CONFIG_DNOTIFY is not set -+CONFIG_AUTOFS4_FS=y - CONFIG_VFAT_FS=y - CONFIG_TMPFS=y - CONFIG_TMPFS_POSIX_ACL=y -@@ -289,7 +299,6 @@ CONFIG_NLS_CODEPAGE_437=y - CONFIG_NLS_ISO8859_1=y - CONFIG_PRINTK_TIME=y - CONFIG_DEBUG_INFO=y --CONFIG_DEBUG_FS=y - CONFIG_MAGIC_SYSRQ=y - CONFIG_DEBUG_SLAB=y - CONFIG_DEBUG_VM=y --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0002-apalis-tk1-temp-alert-pull-up.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0002-apalis-tk1-temp-alert-pull-up.patch deleted file mode 100644 index be59f28..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0002-apalis-tk1-temp-alert-pull-up.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 34ef168249df6e467ecdb0333eef7f95f87ab195 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Tue, 22 Nov 2016 00:57:47 +0100 -Subject: [RESEND PATCH 2/6] apalis-tk1: temp alert pull-up - -Pull-up GPIO_PI6 connected to TMP451's ALERT#/THERM2#. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - - arch/arm/boot/dts/tegra124-apalis.dtsi | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi -index 6aa4952..0534601 100644 ---- a/arch/arm/boot/dts/tegra124-apalis.dtsi -+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi -@@ -1151,11 +1151,11 @@ - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; - -- /* GPIO_PI6 aka TEMP_ALERT_L */ -+ /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ - pi6 { - nvidia,pins = "pi6"; - nvidia,function = "rsvd1"; -- nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0002-igb-integrate-tools-only-device-support.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0002-igb-integrate-tools-only-device-support.patch deleted file mode 100644 index f4e85db..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0002-igb-integrate-tools-only-device-support.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 11901a29054e437c9f9241382512faf276f08df4 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Thu, 15 Dec 2016 10:55:11 +0100 -Subject: [PATCH 2/4] igb: integrate tools only device support - -Springville/i211 with a blank Flash/iNVM use different PCI IDs. Extend -the driver to load despite i210/i211 data sheets claiming tools only, -not for driver. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> - -(cherry picked from toradex_tk1_l4t_r21.5 commit -783780c43fd4e1473fb64790c8b9e0adb2be04a3) -(cherry picked from tegra commit -2c7123458270c9b3ec9b5ed668f9d55a7f8dbad9) - ---- - - drivers/net/ethernet/intel/igb/e1000_82575.c | 2 ++ - drivers/net/ethernet/intel/igb/e1000_hw.h | 2 ++ - drivers/net/ethernet/intel/igb/igb_main.c | 2 ++ - 3 files changed, 6 insertions(+) - -diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c -index a61447f..53d9ae7 100644 ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -610,6 +610,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) - case E1000_DEV_ID_I350_SGMII: - mac->type = e1000_i350; - break; -+ case E1000_DEV_ID_I210_TOOLS_ONLY: - case E1000_DEV_ID_I210_COPPER: - case E1000_DEV_ID_I210_FIBER: - case E1000_DEV_ID_I210_SERDES: -@@ -618,6 +619,7 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) - case E1000_DEV_ID_I210_SERDES_FLASHLESS: - mac->type = e1000_i210; - break; -+ case E1000_DEV_ID_I211_TOOLS_ONLY: - case E1000_DEV_ID_I211_COPPER: - mac->type = e1000_i211; - break; -diff --git a/drivers/net/ethernet/intel/igb/e1000_hw.h b/drivers/net/ethernet/intel/igb/e1000_hw.h -index 2fb2213..69ebb81 100644 ---- a/drivers/net/ethernet/intel/igb/e1000_hw.h -+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h -@@ -58,6 +58,8 @@ struct e1000_hw; - #define E1000_DEV_ID_I350_FIBER 0x1522 - #define E1000_DEV_ID_I350_SERDES 0x1523 - #define E1000_DEV_ID_I350_SGMII 0x1524 -+#define E1000_DEV_ID_I210_TOOLS_ONLY 0x1531 -+#define E1000_DEV_ID_I211_TOOLS_ONLY 0x1532 - #define E1000_DEV_ID_I210_COPPER 0x1533 - #define E1000_DEV_ID_I210_FIBER 0x1536 - #define E1000_DEV_ID_I210_SERDES 0x1537 -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index a761001..680abcd 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -77,7 +77,9 @@ static const struct pci_device_id igb_pci_tbl[] = { - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, -+ { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_TOOLS_ONLY), board_82575 }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, -+ { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_TOOLS_ONLY), board_82575 }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, - { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0003-apalis-tk1-optional-displayport-hot-plug-detect.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0003-apalis-tk1-optional-displayport-hot-plug-detect.patch deleted file mode 100644 index 7adc524..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0003-apalis-tk1-optional-displayport-hot-plug-detect.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 9172020334268e0e49478afd8a520554df3c612c Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Tue, 22 Nov 2016 00:58:26 +0100 -Subject: [RESEND PATCH 3/6] apalis-tk1: optional displayport hot-plug detect - -Configure DP_HPD_PFF0 pin as optional DisplayPort hot-plug detect. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - - arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi -index 0534601..747ce81 100644 ---- a/arch/arm/boot/dts/tegra124-apalis.dtsi -+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi -@@ -255,7 +255,7 @@ - }; - dp_hpd_pff0 { - nvidia,pins = "dp_hpd_pff0"; -- nvidia,function = "rsvd2"; -+ nvidia,function = "dp"; - nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0003-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0003-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch deleted file mode 100644 index cd53bc6..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0003-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch +++ /dev/null @@ -1,136 +0,0 @@ -From 259b864ce38d18f7de945f957ee2e11ea4429812 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Thu, 15 Dec 2016 10:55:54 +0100 -Subject: [PATCH 3/4] apalis_t30/tk1: igb: no nvm and Ethernet MAC address - handling - -Only warn rather than fail on NVM validation failures on Apalis T30 and -Apalis TK1. - -Revise Ethernet MAC address assignment: should now handle up to two -instances of custom user MACs (2nd one with a 0x100000 offset). This -way customer does not have to worry about NVM on a secondary Ethernet -on the carrier board and still gets a valid official MAC address from -us (e.g. analogous to how we did it on our Protea carrier board). - -Use the Toradex OUI as default MAC address if no valid one is -encountered. - -Tested on samples of Apalis T30 2GB V1.0B, V1.0C, V1.1A, Apalis T30 1GB -V1.0A, V1.1A and Apalis T30 1GB IT V1.1A both with blank NVMs as well -as iNVMs programmed with Intel's defaults. - -Tested on samples of Apalis TK1 2GB V1.0A, V1.0B and V1.1A both with -blank NVMs as well as iNVMs programmed with Intel's defaults. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> - -(cherry picked from toradex_tk1_l4t_r21.5 commit -70efa60d96c9f05d91d8875eee97446df7f9e877) -(cherry picked from tegra commit -c4c3c7449bdb15c53bfebb0a29c73b24ea810d23) - ---- - - drivers/net/ethernet/intel/igb/igb_main.c | 60 +++++++++++++++++++++++++++++-- - 1 file changed, 57 insertions(+), 3 deletions(-) - -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index 680abcd..3df0e4e 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -55,6 +55,7 @@ - #include <linux/dca.h> - #endif - #include <linux/i2c.h> -+#include <linux/ctype.h> - #include "igb.h" - - #define MAJ 5 -@@ -69,6 +70,9 @@ static const char igb_driver_string[] = - static const char igb_copyright[] = - "Copyright (c) 2007-2014 Intel Corporation."; - -+static char g_mac_addr[ETH_ALEN]; -+static int g_usr_mac = 0; -+ - static const struct e1000_info *igb_info_tbl[] = { - [board_82575] = &e1000_82575_info, - }; -@@ -258,6 +262,37 @@ static int debug = -1; - module_param(debug, int, 0); - MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); - -+/* Retrieve user set MAC address */ -+static int __init setup_igb_mac(char *macstr) -+{ -+ int i, j; -+ unsigned char result, value; -+ -+ for (i = 0; i < ETH_ALEN; i++) { -+ result = 0; -+ -+ if (i != 5 && *(macstr + 2) != ':') -+ return -1; -+ -+ for (j = 0; j < 2; j++) { -+ if (isxdigit(*macstr) && (value = isdigit(*macstr) ? -+ *macstr - '0' : toupper(*macstr) - 'A' + 10) < 16) { -+ result = result * 16 + value; -+ macstr++; -+ } else -+ return -1; -+ } -+ -+ macstr++; -+ g_mac_addr[i] = result; -+ } -+ -+ g_usr_mac = 1; -+ -+ return 0; -+} -+__setup("igb_mac=", setup_igb_mac); -+ - struct igb_reg_info { - u32 ofs; - char *name; -@@ -2511,12 +2546,31 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) - dev_err(&pdev->dev, "NVM Read Error\n"); - } - -+ if (g_usr_mac && (g_usr_mac < 3)) { -+ /* Get user set MAC address */ -+ if (g_usr_mac == 2) { -+ /* 0x100000 offset for 2nd Ethernet MAC */ -+ g_mac_addr[3] += 0x10; -+ if (g_mac_addr[3] < 0x10) -+ dev_warn(&pdev->dev, -+ "MAC addr byte 3 (0x%02x) wrap around" -+ "\n", -+ g_mac_addr[3]); -+ } -+ memcpy(hw->mac.addr, g_mac_addr, ETH_ALEN); -+ g_usr_mac++; -+ } -+ - memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); - - if (!is_valid_ether_addr(netdev->dev_addr)) { -- dev_err(&pdev->dev, "Invalid MAC Address\n"); -- err = -EIO; -- goto err_eeprom; -+ /* Use Toradex OUI as default */ -+ char default_mac_addr[ETH_ALEN] = { -+ 0x0, 0x14, 0x2d, 0x0, 0x0, 0x0 -+ }; -+ dev_warn(&pdev->dev, "using Toradex OUI as default igb MAC\n"); -+ memcpy(hw->mac.addr, default_mac_addr, ETH_ALEN); -+ memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); - } - - /* get firmware version for ethtool -i */ --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0004-apalis-tk1-adjust-pin-muxing-for-v1.1-hw.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0004-apalis-tk1-adjust-pin-muxing-for-v1.1-hw.patch deleted file mode 100644 index 6841716..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0004-apalis-tk1-adjust-pin-muxing-for-v1.1-hw.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 8c753a8354ae5927667b2a450eab2f49ceaac36b Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Tue, 22 Nov 2016 00:59:43 +0100 -Subject: [RESEND PATCH 4/6] apalis-tk1: adjust pin muxing for v1.1 hw - -Configure Apalis MMC1 D6 GPIO on SDMMC3_CLK_LB_IN as reserved function -without any pull-up/down. - -Configure GPIO_PV2 as SD1_CD# according to latest V1.1 HW. - -Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output driver enabled aka -not tristated and input driver enabled as well as it features some -magic properties even though the external loopback is disabled and the -internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 register's -SDMMC_SPARE1 bits being set to 0xfffd according to the TRM! This pin is -now a not-connect on V1.1 HW in order to avoid any interference. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - - arch/arm/boot/dts/tegra124-apalis.dtsi | 53 +++++++++++++++------------------- - 1 file changed, 23 insertions(+), 30 deletions(-) - -diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi -index 747ce81..2bfc579 100644 ---- a/arch/arm/boot/dts/tegra124-apalis.dtsi -+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi -@@ -414,18 +414,10 @@ - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; -- /* -- * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it -- * features some magic properties even though the -- * external loopback is disabled and the internal -- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 -- * register's SDMMC_SPARE1 bits being set to 0xfffd -- * according to the TRM! -- */ - sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ - nvidia,pins = "sdmmc3_clk_lb_in_pee5"; -- nvidia,function = "sdmmc3"; -- nvidia,pull = <TEGRA_PIN_PULL_UP>; -+ nvidia,function = "rsvd2"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; -@@ -520,20 +512,12 @@ - nvidia,tristate = <TEGRA_PIN_DISABLE>; - nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; -- /* -- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it -- * features some magic properties even though the -- * external loopback is disabled and the internal -- * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0 -- * register's SDMMC_SPARE1 bits being set to 0xfffd -- * according to the TRM! -- */ -- sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */ -- nvidia,pins = "sdmmc3_clk_lb_out_pee4"; -- nvidia,function = "rsvd2"; -- nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ sdmmc3_cd_n_pv2 { /* CD# GPIO */ -+ nvidia,pins = "sdmmc3_cd_n_pv2"; -+ nvidia,function = "rsvd3"; -+ nvidia,pull = <TEGRA_PIN_PULL_UP>; - nvidia,tristate = <TEGRA_PIN_ENABLE>; -- nvidia,enable-input = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; - }; - - /* Apalis SPDIF */ -@@ -1512,13 +1496,6 @@ - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; -- sdmmc3_cd_n_pv2 { /* NC */ -- nvidia,pins = "sdmmc3_cd_n_pv2"; -- nvidia,function = "rsvd3"; -- nvidia,pull = <TEGRA_PIN_PULL_DOWN>; -- nvidia,tristate = <TEGRA_PIN_ENABLE>; -- nvidia,enable-input = <TEGRA_PIN_DISABLE>; -- }; - gpio_x1_aud_px1 { /* NC */ - nvidia,pins = "gpio_x1_aud_px1"; - nvidia,function = "rsvd2"; -@@ -1568,6 +1545,22 @@ - nvidia,tristate = <TEGRA_PIN_ENABLE>; - nvidia,enable-input = <TEGRA_PIN_DISABLE>; - }; -+ /* -+ * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output -+ * driver enabled aka not tristated and input driver -+ * enabled as well as it features some magic properties -+ * even though the external loopback is disabled and the -+ * internal loopback used as per -+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 -+ * bits being set to 0xfffd according to the TRM! -+ */ -+ sdmmc3_clk_lb_out_pee4 { /* NC */ -+ nvidia,pins = "sdmmc3_clk_lb_out_pee4"; -+ nvidia,function = "sdmmc3"; -+ nvidia,pull = <TEGRA_PIN_PULL_NONE>; -+ nvidia,tristate = <TEGRA_PIN_DISABLE>; -+ nvidia,enable-input = <TEGRA_PIN_ENABLE>; -+ }; - }; - }; - --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0004-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0004-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch deleted file mode 100644 index 9426107..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0004-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 3012bd5c49b1f0ce750767194f76e556fbe7e6e6 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Thu, 15 Dec 2016 10:56:26 +0100 -Subject: [PATCH 4/4] mmc: tegra: apalis-tk1: hack to make sd1 functional - -Disable the external loopback and use the internal loopback as per -SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to -0xfffd according to the TRM. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Acked-by: Dominik Sliwa <dominik.sliwa@toradex.com> - -(cherry picked from toradex_tk1_l4t_r21.5 commit -fc14b7601e5ca587afd97936ef3fd599f4e9281c) - ---- - - drivers/mmc/host/sdhci-tegra.c | 11 +++++++++++ - 1 file changed, 11 insertions(+) - -diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c -index 20b6ff5..6c84334 100644 ---- a/drivers/mmc/host/sdhci-tegra.c -+++ b/drivers/mmc/host/sdhci-tegra.c -@@ -42,6 +42,7 @@ - #define SDHCI_MISC_CTRL_ENABLE_SDR50 0x10 - #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 - #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 -+#define SDHCI_MISC_CTRL_ENABLE_EXT_LOOPBACK 0x20000 - - #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 - #define SDHCI_AUTO_CAL_START BIT(31) -@@ -178,6 +179,16 @@ static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask) - clk_ctrl |= SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE; - } - -+#define CONFIG_MACH_APALIS_TK1 -+#ifdef CONFIG_MACH_APALIS_TK1 -+ /* -+ * Disable the external loopback and use the internal loopback as per -+ * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being set to -+ * 0xfffd according to the TRM. -+ */ -+ misc_ctrl &= ~SDHCI_MISC_CTRL_ENABLE_EXT_LOOPBACK; -+#endif /* CONFIG_MACH_APALIS_TK1 */ -+ - sdhci_writel(host, misc_ctrl, SDHCI_TEGRA_VENDOR_MISC_CTRL); - sdhci_writel(host, clk_ctrl, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); - --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0005-apalis-tk1-working-sd-card-detect-on-v1.1-hw.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0005-apalis-tk1-working-sd-card-detect-on-v1.1-hw.patch deleted file mode 100644 index 1a091dd..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0005-apalis-tk1-working-sd-card-detect-on-v1.1-hw.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 042f3f04daed2a1163a5b35b47ab8c9a8e6bf29d Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Tue, 22 Nov 2016 01:00:50 +0100 -Subject: [RESEND PATCH 5/6] apalis-tk1: working sd card detect on v1.1 hw - -Add sd card detect SD1_CD# applicable for V1.1 modules using GPIO_PV2. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - - arch/arm/boot/dts/tegra124-apalis-eval.dts | 10 ++-------- - 1 file changed, 2 insertions(+), 8 deletions(-) - -diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts -index 2b5a0f3..2715692 100644 ---- a/arch/arm/boot/dts/tegra124-apalis-eval.dts -+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts -@@ -187,14 +187,8 @@ - /* Apalis SD1 */ - sdhci@700b0400 { - status = "okay"; -- /* -- * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it -- * features some magic properties even though the external -- * loopback is disabled and the internal loopback used as per -- * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being -- * set to 0xfffd according to the TRM! -- * cd-gpios = <&gpio TEGRA_GPIO(EE, 4) GPIO_ACTIVE_LOW>; -- */ -+ /* SD1_CD# */ -+ cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - bus-width = <4>; - vqmmc-supply = <&vddio_sdmmc3>; - }; --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline-4.9/0006-apalis-tk1-update-compatibility-comment.patch b/recipes-kernel/linux/linux-toradex-mainline-4.9/0006-apalis-tk1-update-compatibility-comment.patch deleted file mode 100644 index 71743aa..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline-4.9/0006-apalis-tk1-update-compatibility-comment.patch +++ /dev/null @@ -1,30 +0,0 @@ -From e73b61059b07d263d76a887f0354cbdb108a47b8 Mon Sep 17 00:00:00 2001 -From: Marcel Ziswiler <marcel.ziswiler@toradex.com> -Date: Thu, 24 Nov 2016 01:35:48 +0100 -Subject: [RESEND PATCH 6/6] apalis-tk1: update compatibility comment - -Now with the new V1.1A HW card detect being implemented update resp. -compatibility information. - -Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> ---- - - arch/arm/boot/dts/tegra124-apalis.dtsi | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi -index 2bfc579..2276073 100644 ---- a/arch/arm/boot/dts/tegra124-apalis.dtsi -+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi -@@ -44,7 +44,7 @@ - - /* - * Toradex Apalis TK1 Module Device Tree -- * Compatible for Revisions 2GB: V1.0A -+ * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A - */ - / { - model = "Toradex Apalis TK1"; --- -2.9.3 - diff --git a/recipes-kernel/linux/linux-toradex-mainline_4.14.bb b/recipes-kernel/linux/linux-toradex-mainline_4.14.bb index a9cc2a9..7abc4cf 100644 --- a/recipes-kernel/linux/linux-toradex-mainline_4.14.bb +++ b/recipes-kernel/linux/linux-toradex-mainline_4.14.bb @@ -9,7 +9,7 @@ LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" inherit kernel siteinfo include conf/tdx_version.conf -LINUX_VERSION ?= "4.14.54" +LINUX_VERSION ?= "4.14.72" LOCALVERSION = "-${PR}" PR = "${TDX_VER_ITEM}" @@ -60,8 +60,8 @@ SRC_URI = " \ ${GENERIC_PATCHES} \ ${MACHINE_PATCHES} \ " -SRC_URI[md5sum] = "c998ee20fe479707c0a40346f0d6e42c" -SRC_URI[sha256sum] = "451642ac28c539a91072f1fb83b1c061d6d44df870ddf5562400ade5e1c4b6c6" +SRC_URI[md5sum] = "450b3f5f1124442dee768eaa097fd149" +SRC_URI[sha256sum] = "df925906250bbc40fcf0137d7ad0fb8edc528d926832634f1233b7540564557f" # For CI use one could use the following instead (plus patches still of course) LINUX_VERSION_use-head-next ?= "4.14" diff --git a/recipes-kernel/linux/linux-toradex-mainline_4.9.bb b/recipes-kernel/linux/linux-toradex-mainline_4.9.bb deleted file mode 100644 index ee8f4dc..0000000 --- a/recipes-kernel/linux/linux-toradex-mainline_4.9.bb +++ /dev/null @@ -1,79 +0,0 @@ -SUMMARY = "Linux Kernel for Toradex Apalis Tegra based modules" -SECTION = "kernel" -LICENSE = "GPLv2" - -FILESEXTRAPATHS_prepend := "${THISDIR}/linux-toradex-mainline-4.9:" - -LIC_FILES_CHKSUM = "file://COPYING;md5=d7810fab7487fb0aad327b76f1be7cd7" - -inherit kernel siteinfo -include conf/tdx_version.conf - -LINUX_VERSION ?= "4.9.52" - -LOCALVERSION = "-${PR}" -PR = "${TDX_VER_ITEM}" - -PV = "${LINUX_VERSION}" -S = "${WORKDIR}/linux-${PV}" -TK1-PATCHES = " \ - file://0001-toradex_apalis_tk1_t30-customize-defconfig.patch \ - file://0001-apalis-tk1-remove-spurious-new-lines.patch \ - file://0002-apalis-tk1-temp-alert-pull-up.patch \ - file://0003-apalis-tk1-optional-displayport-hot-plug-detect.patch \ - file://0004-apalis-tk1-adjust-pin-muxing-for-v1.1-hw.patch \ - file://0005-apalis-tk1-working-sd-card-detect-on-v1.1-hw.patch \ - file://0006-apalis-tk1-update-compatibility-comment.patch \ - file://0001-apalis_t30-tk1-fix-pcie-clock-and-reset-not-conformi.patch \ - file://0002-igb-integrate-tools-only-device-support.patch \ - file://0003-apalis_t30-tk1-igb-no-nvm-and-Ethernet-MAC-address-h.patch \ - file://0004-mmc-tegra-apalis-tk1-hack-to-make-sd1-functional.patch \ - file://0001-drm-tegra-add-tiling-FB-modifiers.patch \ - file://0001-tegra_defconfig-snapd-squashfs-configuration.patch \ - file://0001-ARM-tegra-apalis-tk1-support-v1.2-hardware-revision.patch \ -" -SRC_URI = " \ - https://cdn.kernel.org/pub/linux/kernel/v4.x/linux-${PV}.tar.xz \ - ${TK1-PATCHES} \ -" -SRC_URI[md5sum] = "3752317fdacdb9b341ae3e500481eb3a" -SRC_URI[sha256sum] = "ffdd034f1bf32fa41d1a66a347388c0dc4c3cff6f578a1e29d88b20fbae1048a" - -# For CI use one could use the following instead (plus patches still of course) -LINUX_VERSION_use-head-next ?= "4.9" -SRCREV_use-head-next = "${AUTOREV}" -PV_use-head-next = "${LINUX_VERSION}+git${SRCPV}" -S_use-head-next = "${WORKDIR}/git" -SRCBRANCH_use-head-next = "linux-4.9.y" -SRC_URI_use-head-next = " \ - git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git;protocol=git;branch=${SRCBRANCH} \ - ${TK1-PATCHES} \ -" - -COMPATIBLE_MACHINE = "(apalis-tk1-mainline|apalis-t30-mainline)" -KERNEL_EXTRA_ARGS = " LOADADDR=0x80008000 " - -# One possibiltiy for changes to the defconfig: -config_script () { - echo "dummy" > /dev/null -} - -do_configure_prepend () { - cd ${S} - export KBUILD_OUTPUT=${B} - oe_runmake ${KERNEL_DEFCONFIG} - - #maybe change some configuration - config_script - - #Add Toradex BSP Version as LOCALVERSION - sed -i -e /CONFIG_LOCALVERSION/d ${B}/.config - echo "CONFIG_LOCALVERSION=\"${LOCALVERSION}\"" >> ${B}/.config - - cd - > /dev/null -} - -do_uboot_mkimage_prepend() { - cd ${B} -} - diff --git a/recipes-kernel/linux/linux-toradex_3.10.40.bb b/recipes-kernel/linux/linux-toradex_3.10.40.bb index e6a3990..a8304c4 100644 --- a/recipes-kernel/linux/linux-toradex_3.10.40.bb +++ b/recipes-kernel/linux/linux-toradex_3.10.40.bb @@ -12,7 +12,7 @@ LINUX_VERSION ?= "3.10.40" LOCALVERSION = "-${PR}" PR = "${TDX_VER_ITEM}" -SRCREV = "6c533d394e9f65d1f2b1075a5169c8c33d623c9a" +SRCREV = "ba29b069a970c97be7255b3f42176be620f6ea70" SRCREV_use-head-next = "${AUTOREV}" PV = "${LINUX_VERSION}+gitr${SRCPV}" diff --git a/recipes-kernel/linux/linux-toradex_git.bb b/recipes-kernel/linux/linux-toradex_git.bb index 033273e..6be2f60 100644 --- a/recipes-kernel/linux/linux-toradex_git.bb +++ b/recipes-kernel/linux/linux-toradex_git.bb @@ -7,7 +7,7 @@ LINUX_VERSION ?= "3.1.10" LOCALVERSION = "-${PR}" PR = "${TDX_VER_ITEM}" -SRCREV = "ab054f54393989e52ff31f3539d17f233021f0f9" +SRCREV = "2a1eb198705c855be56f2d237f9c99edbff167e3" SRCREV_use-head-next = "${AUTOREV}" PV = "${LINUX_VERSION}+gitr${SRCPV}" |