colibri_vf: implement module type auto detection

Implement module type (e.g. VF50 vs. VF61) auto detection based on L2
cache availability. Set specific ARM core clock (e.g. 400 vs. 500 MHz)
as well as Linux machine id number.

While at it actually use memargs instead of hard-coded mem= value.

While at it fix sdboot command if initially booting U-Boot from NAND by
doing an explicit mmc part 0.

7 files changed, 52 insertions, 11 deletions

diff --git a/arch/arm/cpu/armv7/vybrid-common/cpu.c b/arch/arm/cpu/armv7/vybrid-common/cpu.c
index 865c01fc58..4c2dcfe0fa 100644
--- a/arch/arm/cpu/armv7/vybrid-common/cpu.c
+++ b/arch/arm/cpu/armv7/vybrid-common/cpu.c
@@ -103,7 +103,11 @@ int print_cpuinfo(void)
 		(cpurev & 0xFFF000) >> 12,
 		(cpurev & 0x000F0) >> 4,
 		(cpurev & 0x0000F) >> 0,
+#ifdef CONFIG_AUTO_DETECT_FREQUENCY
+		__raw_readl(MSCM_CP0CFG1)?500:400);
+#else
 		vybrid_get_clock(VYBRID_ARM_CLK) / 1000000);
+#endif
 	if (get_reset_cause() != NULL)
 		printf("Reset cause: %s\n", get_reset_cause());
 	return 0;
diff --git a/arch/arm/cpu/armv7/vybrid-common/speed.c b/arch/arm/cpu/armv7/vybrid-common/speed.c
index df768b37e4..7983063479 100644
--- a/arch/arm/cpu/armv7/vybrid-common/speed.c
+++ b/arch/arm/cpu/armv7/vybrid-common/speed.c
@@ -33,7 +33,12 @@ DECLARE_GLOBAL_DATA_PTR;
 int get_clocks(void)
 {
 	gd->bus_clk = 66000000;
-	gd->ipg_clk = 66000000;
+#ifdef CONFIG_AUTO_DETECT_FREQUENCY
+	if (__raw_readl(MSCM_CP0CFG1))
+		gd->ipg_clk = 83000000;
+	else
+#endif
+		gd->ipg_clk = 66000000;
 #ifdef CONFIG_FSL_ESDHC
 	gd->sdhc_clk = 132000000;
 #endif
diff --git a/arch/arm/cpu/armv7/vybrid/clock.c b/arch/arm/cpu/armv7/vybrid/clock.c
index eea6af0f57..190333943e 100644
--- a/arch/arm/cpu/armv7/vybrid/clock.c
+++ b/arch/arm/cpu/armv7/vybrid/clock.c
@@ -176,7 +176,12 @@ static u32 get_ipg_clk(void)
 
 	return freq / div;
 #else
-	return 66000000;
+#ifdef CONFIG_AUTO_DETECT_FREQUENCY
+	if (__raw_readl(MSCM_CP0CFG1))
+		return 83000000;
+	else
+#endif
+		return 66000000;
 #endif
 }
 
diff --git a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
index 8c22e3c365..630e4a8efe 100644
--- a/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/vybrid/lowlevel_init.S
@@ -132,7 +132,17 @@
 	ldr r1, =CONFIG_SYS_CLKCTRL_CCR
 	str r1, [r0, #CLKCTL_CCR]
 
+#ifdef CONFIG_AUTO_DETECT_FREQUENCY
+	/* check for L2 cache */
+	ldr r2, =MSCM_BASE_ADDR
+	ldr r1, [r2, #MSCM_CP0CFG1_OFFSET]
+	cmp r1, #0x0
+	ldr r1, =CONFIG_SYS_CLKCTRL_CCSR_400
+	/* use 500 MHz if L2 cache present (Colibri VF61) */
+	ldrne r1, =CONFIG_SYS_CLKCTRL_CCSR_500
+#else /* CONFIG_AUTO_DETECT_FREQUENCY */
 	ldr r1, =CONFIG_SYS_CLKCTRL_CCSR
+#endif /* CONFIG_AUTO_DETECT_FREQUENCY */
 	str r1, [r0, #CLKCTL_CCSR]
 
 	ldr r1, =CONFIG_SYS_CLKCTRL_CACRR
diff --git a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
index d1647f0c18..19ab3731c0 100644
--- a/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
+++ b/arch/arm/include/asm/arch-vybrid/vybrid-regs.h
@@ -103,6 +103,9 @@
 #define MACNET0_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00050000)
 #define MACNET1_BASE_ADDR	(AIPS1_BASE_ADDR + 0x00051000)
 
+#define MSCM_CP0CFG1_OFFSET	0x14
+#define MSCM_CP0CFG1		(MSCM_BASE_ADDR + MSCM_CP0CFG1_OFFSET)
+
 /* WEIM CSnGCR1 */
 #define CSEN			1
 #define SWR			(1 << 1)
diff --git a/board/toradex/colibri_vf61/colibri_vf61.c b/board/toradex/colibri_vf61/colibri_vf61.c
index 35c8f7768c..97eaa9e6c4 100644
--- a/board/toradex/colibri_vf61/colibri_vf61.c
+++ b/board/toradex/colibri_vf61/colibri_vf61.c
@@ -212,7 +212,10 @@ int board_mmc_init(bd_t *bis)
 
 int checkboard(void)
 {
-	puts("Board: Colibri VF61\n");
+	if (__raw_readl(MSCM_CP0CFG1))
+		puts("Board: Colibri VF61\n");
+	else
+		puts("Board: Colibri VF50\n");
 
 	return 0;
 }
diff --git a/include/configs/colibri_vf61.h b/include/configs/colibri_vf61.h
index e476f3998e..b59da572df 100644
--- a/include/configs/colibri_vf61.h
+++ b/include/configs/colibri_vf61.h
@@ -1,7 +1,8 @@
 /*
  * Copyright 2013 Toradex, Inc.
  *
- * Configuration settings for the Colibri VF61 module booting from NAND flash.
+ * Configuration settings for the Colibri VF50 and VF61 modules
+ * booting from NAND flash.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -50,7 +51,8 @@
 
 #undef CONFIG_OF_LIBFDT
 
-#define CONFIG_MACH_TYPE		MACH_TYPE_COLIBRI_VF61
+#define CONFIG_AUTO_DETECT_FREQUENCY
+#define CONFIG_MACH_TYPE		(__raw_readl(MSCM_CP0CFG1)?MACH_TYPE_COLIBRI_VF61:MACH_TYPE_COLIBRI_VF50)
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 4 * 1024 * 1024)
 
@@ -152,7 +154,7 @@
 	"run setup; "						\
 	"setenv bootargs ${defargs} ${mmcargs} ${mtdparts} ${setupargs}; " \
 	"echo Booting from MMC/SD card...; "			\
-	"fatload mmc 0:1 ${loadaddr} uImage && bootm"
+	"mmc part 0; fatload mmc 0:1 ${loadaddr} uImage && bootm"
 
 #define NFS_BOOTCMD						\
 	"run setup; "						\
@@ -170,14 +172,14 @@
 #define CONFIG_NFSBOOTCOMMAND	NFS_BOOTCMD
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-	"defargs=vmalloc=64M mem=256M usb_high_speed=1\0" \
+	"defargs=vmalloc=64M usb_high_speed=1\0" \
 	"mmcargs=root=/dev/mmcblk0p2 rw rootwait\0" \
 	"sdboot=" MMC_BOOTCMD "\0" \
 	"mtdparts=" MTDPARTS_DEFAULT "\0" \
 	"nfsargs=ip=:::::eth0: root=/dev/nfs\0" \
 	"setup=setenv setupargs " \
 	"fec_mac=${ethaddr} no_console_suspend=1 console=tty1 console=ttymxc0" \
-		",${baudrate}n8\0" \
+		",${baudrate}n8 ${memargs}\0" \
 	"ubiargs=ubi.mtd=5 root=ubi0:rootfs rootfstype=ubifs\0" \
 	"ubiboot=" UBI_BOOTCMD "\0" \
 	""
@@ -238,7 +240,7 @@
 #define CONFIG_SYS_LONGHELP		/* undef to save memory */
 #define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_PROMPT		"Colibri VF61 # "
+#define CONFIG_SYS_PROMPT		"Colibri VFxx # "
 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE		\
@@ -265,7 +267,6 @@
 
 /* Physical Memory Map */
 #define CONFIG_NR_DRAM_BANKS		1
-#define PHYS_SDRAM_1_SIZE		(256 * 1024 * 1024)
 
 #define CONFIG_SYS_SDRAM_BASE		(0x80000000)
 #define CONFIG_SYS_INIT_RAM_ADDR	(IRAM_BASE_ADDR)
@@ -298,10 +299,20 @@
 
 #define CONFIG_SYS_CLKCTRL_CCR		0x00010005
 /* 10.2.3 CCM Clock Switcher Register (CCM_CCSR) */
+//PLL1_PFD_CLK_SEL:
+//001 PLL1 PFD1 clock = 500 MHz
+//010 PLL1 PFD2 clock
+//011 PLL1 PFD3 clock = 396 MHz
+//100 PLL1 PFD4 clock
 //DDRC_CLK_SEL: PLL2 PFD2 clk
 //PLL2 (PLL 528 MHz)
 //PFD2 396 MHz
-#define CONFIG_SYS_CLKCTRL_CCSR		0x0003FF24
+#define CONFIG_SYS_CLKCTRL_CCSR_400		0x0003FF24
+#define CONFIG_SYS_CLKCTRL_CCSR_500		0x0001FF24
+//10.2.4 CCM ARM Clock Root Register (CCM_CACRR)
+//ARM_CLK_DIV = 1 => 396 resp. 500 MHz
+//BUS_CLK_DIV = 3 => 132 resp. 166 MHz
+//IPG_CLK_DIV = 2 => 66 resp. 83 MHz
 #define CONFIG_SYS_CLKCTRL_CACRR	0x00000810
 #define CONFIG_SYS_CLKCTRL_CSCMR1	0x03CA0000
 #define CONFIG_SYS_CLKCTRL_CSCDR1	0x01000000