tegra: lcd: video: integrate display driver for t30

On popular request make the display driver from T20 work on T30 as
well. Turned out to be quite straight forward. However a few notes
about some things encountered during porting: Of course the T30 device
tree was completely missing host1x as well as PWM support but it turns
out this can simply be copied from T20. The only trouble compiling the
Tegra video driver for T30 had to do with some hard-coded PWM pin
muxing for T20 which is quite ugly anyway. On T30 this gets handled by
a board specific complete pin muxing table. The older Chromium U-Boot
2011.06 which to my knowledge was the only prior attempt at enabling a
display driver for T30 for whatever reason got some clocking stuff
mixed up. Turns out at least for a single display controller T20 and
T30 can be clocked quite similar. Enjoy.

11 files changed, 120 insertions, 14 deletions

diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi
index 5ea7e347f3..ca00b15ea2 100644
--- a/arch/arm/dts/tegra30.dtsi
+++ b/arch/arm/dts/tegra30.dtsi
@@ -8,6 +8,104 @@
 	compatible = "nvidia,tegra30";
 	interrupt-parent = <&intc>;
 
+	host1x {
+		compatible = "nvidia,tegra20-host1x", "simple-bus";
+		reg = <0x50000000 0x00024000>;
+		interrupts = <0 65 0x04   /* mpcore syncpt */
+			      0 67 0x04>; /* mpcore general */
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ranges = <0x54000000 0x54000000 0x04000000>;
+
+		/* video-encoding/decoding */
+		mpe {
+			reg = <0x54040000 0x00040000>;
+			interrupts = <0 68 0x04>;
+			status = "disabled";
+		};
+
+		/* video input */
+		vi {
+			reg = <0x54080000 0x00040000>;
+			interrupts = <0 69 0x04>;
+			status = "disabled";
+		};
+
+		/* EPP */
+		epp {
+			reg = <0x540c0000 0x00040000>;
+			interrupts = <0 70 0x04>;
+			status = "disabled";
+		};
+
+		/* ISP */
+		isp {
+			reg = <0x54100000 0x00040000>;
+			interrupts = <0 71 0x04>;
+			status = "disabled";
+		};
+
+		/* 2D engine */
+		gr2d {
+			reg = <0x54140000 0x00040000>;
+			interrupts = <0 72 0x04>;
+			status = "disabled";
+		};
+
+		/* 3D engine */
+		gr3d {
+			reg = <0x54180000 0x00040000>;
+			status = "disabled";
+		};
+
+		/* display controllers */
+		dc@54200000 {
+			compatible = "nvidia,tegra20-dc";
+			reg = <0x54200000 0x00040000>;
+			interrupts = <0 73 0x04>;
+			status = "disabled";
+
+			rgb {
+				status = "disabled";
+			};
+		};
+
+		dc@54240000 {
+			compatible = "nvidia,tegra20-dc";
+			reg = <0x54240000 0x00040000>;
+			interrupts = <0 74 0x04>;
+			status = "disabled";
+
+			rgb {
+				status = "disabled";
+			};
+		};
+
+		/* outputs */
+		hdmi {
+			compatible = "nvidia,tegra20-hdmi";
+			reg = <0x54280000 0x00040000>;
+			interrupts = <0 75 0x04>;
+			status = "disabled";
+		};
+
+		tvo {
+			compatible = "nvidia,tegra20-tvo";
+			reg = <0x542c0000 0x00040000>;
+			interrupts = <0 76 0x04>;
+			status = "disabled";
+		};
+
+		dsi {
+			compatible = "nvidia,tegra20-dsi";
+			reg = <0x54300000 0x00040000>;
+			status = "disabled";
+		};
+	};
+
 	intc: interrupt-controller@50041000 {
 		compatible = "arm,cortex-a9-gic";
 		reg = <0x50041000 0x1000
@@ -271,6 +369,12 @@
 		status = "disabled";
 	};
 
+	pwm: pwm@7000a000 {
+		compatible = "nvidia,tegra20-pwm";
+		reg = <0x7000a000 0x100>;
+		#pwm-cells = <2>;
+	};
+
 	spi@7000d400 {
 		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
 		reg = <0x7000d400 0x200>;
diff --git a/arch/arm/include/asm/arch-tegra20/dc.h b/arch/arm/include/asm/arch-tegra/dc.h
index 20790b6c0e..20790b6c0e 100644
--- a/arch/arm/include/asm/arch-tegra20/dc.h
+++ b/arch/arm/include/asm/arch-tegra/dc.h
diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra/display.h
index 6feeda3ba8..018c9f9f76 100644
--- a/arch/arm/include/asm/arch-tegra20/display.h
+++ b/arch/arm/include/asm/arch-tegra/display.h
@@ -8,7 +8,7 @@
 #ifndef __ASM_ARCH_TEGRA_DISPLAY_H
 #define __ASM_ARCH_TEGRA_DISPLAY_H
 
-#include <asm/arch/dc.h>
+#include <asm/arch-tegra/dc.h>
 #include <fdtdec.h>
 #include <asm/gpio.h>
 
diff --git a/arch/arm/include/asm/arch-tegra20/pwm.h b/arch/arm/include/asm/arch-tegra/pwm.h
index 8e7397d0e5..8e7397d0e5 100644
--- a/arch/arm/include/asm/arch-tegra20/pwm.h
+++ b/arch/arm/include/asm/arch-tegra/pwm.h
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 04cef0a252..76fdba8a1e 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,6 +12,8 @@ obj-y += spl.o
 obj-y += cpu.o
 else
 obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
+obj-$(CONFIG_PWM_TEGRA) += pwm.o
+obj-$(CONFIG_VIDEO_TEGRA) += display.o
 endif
 
 obj-y += ap.o
diff --git a/arch/arm/mach-tegra/tegra20/display.c b/arch/arm/mach-tegra/display.c
index 61efed6464..efe65573db 100644
--- a/arch/arm/mach-tegra/tegra20/display.c
+++ b/arch/arm/mach-tegra/display.c
@@ -9,8 +9,8 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/tegra.h>
-#include <asm/arch/display.h>
-#include <asm/arch/dc.h>
+#include <asm/arch-tegra/display.h>
+#include <asm/arch-tegra/dc.h>
 #include <asm/arch-tegra/clk_rst.h>
 #include <asm/arch-tegra/timer.h>
 
diff --git a/arch/arm/mach-tegra/tegra20/pwm.c b/arch/arm/mach-tegra/pwm.c
index 5b886363f8..d783576f41 100644
--- a/arch/arm/mach-tegra/tegra20/pwm.c
+++ b/arch/arm/mach-tegra/pwm.c
@@ -10,7 +10,7 @@
 #include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/pwm.h>
+#include <asm/arch-tegra/pwm.h>
 
 struct pwm_info {
 	struct pwm_ctlr *pwm;		/* Registers for our pwm controller */
diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index d48f9bb325..fbf512df71 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -4,12 +4,7 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-ifdef CONFIG_SPL_BUILD
-obj-y	+= cpu.o
-else
-obj-$(CONFIG_PWM_TEGRA) += pwm.o
-obj-$(CONFIG_VIDEO_TEGRA) += display.o
-endif
+obj-$(CONFIG_SPL_BUILD) += cpu.o
 
 # The AVP is ARMv4T architecture so we must use special compiler
 # flags for any startup files it might use.
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
index ca44cd4034..ef1c93f0b3 100644
--- a/board/nvidia/common/board.c
+++ b/board/nvidia/common/board.c
@@ -12,13 +12,13 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #ifdef CONFIG_LCD
-#include <asm/arch/display.h>
+#include <asm/arch-tegra/display.h>
 #endif
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/pmu.h>
 #ifdef CONFIG_PWM_TEGRA
-#include <asm/arch/pwm.h>
+#include <asm/arch-tegra/pwm.h>
 #endif
 #include <asm/arch/tegra.h>
 #include <asm/arch-tegra/ap.h>
diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c
index b8f3431f24..5a5afb9413 100644
--- a/drivers/video/tegra.c
+++ b/drivers/video/tegra.c
@@ -13,8 +13,8 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/funcmux.h>
 #include <asm/arch/pinmux.h>
-#include <asm/arch/pwm.h>
-#include <asm/arch/display.h>
+#include <asm/arch-tegra/pwm.h>
+#include <asm/arch-tegra/display.h>
 #include <asm/arch-tegra/timer.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -215,8 +215,10 @@ static int handle_stage(const void *blob)
 		break;
 	case STAGE_PWM:
 		/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
+#ifdef CONFIG_MACH_T20
 		pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
 		pinmux_tristate_disable(PMUX_PINGRP_GPU);
+#endif
 
 		pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
 		break;
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index bfdbeb70d2..a697e2d49d 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -73,6 +73,9 @@
 #define CONFIG_SYS_SPL_MALLOC_START	0x80090000
 #define CONFIG_SPL_STACK		0x800ffffc
 
+/* Align LCD to 1MB boundary */
+#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
+
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10