diff options
| author | Rajashekhara, Sudhakar <sudhakar.raj@ti.com> | 2012-07-10 13:41:46 +0530 |
|---|---|---|
| committer | Rajashekhara, Sudhakar <sudhakar.raj@ti.com> | 2012-07-10 13:41:46 +0530 |
| commit | 67ae04a9d961d03e98241de7105f2c5a5f445732 (patch) | |
| tree | f30af3a470aecb47c702a9cab965422552fd99a3 | |
| parent | 269d186ab8eb3ad22d4fa89b159d02c060b95be7 (diff) | |
da850/omapl138: configure pll1_sysclk3 within allowable limits2012.04-davinci-ts1
Currently PLL1_SYSCLK3 clock is being configured to 88MHz but the latest
OMAP-L138 data sheet (http://www.ti.com/lit/ds/symlink/omap-l138.pdf)
restricts this frequency to maximum of 75MHz. This patch modifies the
PLL divider and configures PLL1_SYSCLK3 to 66MHz.
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
| -rw-r--r-- | include/configs/da850evm.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 947a9509e7..ac25615f74 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -99,7 +99,7 @@ #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 -#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 +#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8003 #define CONFIG_SYS_DA850_PLL0_PLLM 24 #define CONFIG_SYS_DA850_PLL1_PLLM 21 |