diff options
| author | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2010-11-03 13:15:23 +0530 |
|---|---|---|
| committer | Sudhakar Rajashekhara <sudhakar.raj@ti.com> | 2010-11-03 13:15:23 +0530 |
| commit | eab9d7e640fd85ebdafb31e57255c8a21149c7a8 (patch) | |
| tree | 7ad22931f1eb5aea6061f9e867b60fbee38ea8bc | |
| parent | 978955ff4a9771e888b3e99039513fc5f671c419 (diff) | |
da8xx/omap-l1: modifications for Logic PD Rev.3 AM18xx EVM2009.11-omapl138-201011030745
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will. When
GP0[11] is high, SD0 will work but NOR flash will not.
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
| -rw-r--r-- | board/davinci/da8xxevm/da850evm.c | 25 | ||||
| -rw-r--r-- | include/asm-arm/arch-davinci/hardware.h | 4 |
2 files changed, 29 insertions, 0 deletions
diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index fbf9c2af34..0a63cc2a19 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -65,6 +65,8 @@ const struct pinmux_config spi1_pins[] = { #ifdef CONFIG_DAVINCI_MMC /* SPI0 pin muxer settings */ const struct pinmux_config mmc0_pins[] = { + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux[0], 8, 4 }, /* GP0[11] */ { pinmux[10], 2, 0 }, /* MMCSD0_CLK */ { pinmux[10], 2, 1 }, /* MMCSD0_CMD */ { pinmux[10], 2, 2 }, /* MMCSD0_DAT_0 */ @@ -140,6 +142,8 @@ const struct pinmux_config aemif_pins[] = { }; #elif defined(CONFIG_SYS_USE_NOR) const struct pinmux_config nor_pins[] = { + /* GP0[11] is required for SD to work on Rev 3 EVMs */ + { pinmux[0], 8, 4 }, /* GP0[11] */ { pinmux[5], 1, 6 }, { pinmux[6], 1, 6 }, { pinmux[7], 1, 0 }, @@ -190,6 +194,7 @@ const struct pinmux_config nor_pins[] = { int board_init(void) { + unsigned int temp; #ifndef CONFIG_USE_IRQ /* * Mask all IRQs by clearing the global enable and setting @@ -241,6 +246,16 @@ int board_init(void) #ifdef CONFIG_DAVINCI_MMC if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0) return 1; + + /* Set the GPIO direction as output */ + temp = REG(GPIO_BANK0_REG_DIR_ADDR); + temp &= ~(0x01 << 11); + REG(GPIO_BANK0_REG_DIR_ADDR) = temp; + + /* Set the output as high */ + temp = REG(GPIO_BANK0_REG_SET_ADDR); + temp |= (0x01 << 11); + REG(GPIO_BANK0_REG_SET_ADDR) = temp; #endif if (davinci_configure_pin_mux(uart_pins, ARRAY_SIZE(uart_pins)) != 0) @@ -267,6 +282,16 @@ int board_init(void) #elif defined(CONFIG_SYS_USE_NOR) if (davinci_configure_pin_mux(nor_pins, ARRAY_SIZE(nor_pins)) != 0) return 1; + + /* Set the GPIO direction as output */ + temp = REG(GPIO_BANK0_REG_DIR_ADDR); + temp &= ~(0x01 << 11); + REG(GPIO_BANK0_REG_DIR_ADDR) = temp; + + /* Set the output as low */ + temp = REG(GPIO_BANK0_REG_SET_ADDR); + temp |= (0x01 << 11); + REG(GPIO_BANK0_REG_CLR_ADDR) = temp; #endif /* enable the console UART */ diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index a14845faf1..b4593cd61e 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -157,6 +157,10 @@ typedef volatile unsigned int * dv_reg_p; #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define CFGCHIP3 (DAVINCI_BOOTCFG_BASE + 0x188) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) +#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10) +#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14) +#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18) +#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) |