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authorBhuvanchandra DV <bhuvanchandra.dv@toradex.com>2015-07-29 13:56:54 +0200
committerStefan Agner <stefan.agner@toradex.com>2015-08-10 16:00:09 +0200
commit6cfaccd9320fa2a7c8b4eab9eb7d209ee5f41e5c (patch)
tree582f0dead8abdee6fd3131cf6e3991bd7cb9aa16
parent8b81ce5049a03a50438ab9d21eb60cfbb9f11e60 (diff)
arm: vf610: Add clock support for DSPI
Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
-rw-r--r--arch/arm/cpu/armv7/vf610/generic.c7
-rw-r--r--arch/arm/include/asm/arch-vf610/clock.h1
-rw-r--r--arch/arm/include/asm/arch-vf610/crm_regs.h6
3 files changed, 13 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index fdeabddfd8..c779aeda79 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -199,6 +199,11 @@ static u32 get_i2c_clk(void)
return get_ipg_clk();
}
+static u32 get_dspi_clk(void)
+{
+ return get_ipg_clk();
+}
+
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
@@ -216,6 +221,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
return get_fec_clk();
case MXC_I2C_CLK:
return get_i2c_clk();
+ case MXC_DSPI_CLK:
+ return get_dspi_clk();
default:
break;
}
diff --git a/arch/arm/include/asm/arch-vf610/clock.h b/arch/arm/include/asm/arch-vf610/clock.h
index 535adadd79..e5a5c6d28f 100644
--- a/arch/arm/include/asm/arch-vf610/clock.h
+++ b/arch/arm/include/asm/arch-vf610/clock.h
@@ -17,6 +17,7 @@ enum mxc_clock {
MXC_ESDHC_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
+ MXC_DSPI_CLK,
};
void enable_ocotp_clk(unsigned char enable);
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 0f9515fe43..d588fad158 100644
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -204,7 +204,9 @@ struct anadig_reg {
#define CCM_CCGR0_UART0_CTRL_MASK (0x3 << 14)
#define CCM_CCGR0_UART1_CTRL_MASK (0x3 << 16)
#define CCM_CCGR0_UART2_CTRL_MASK (0x3 << 18)
-#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
+#define CCM_CCGR0_DSPI0_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK (0x3 << 26)
+#define CCM_CCGR1_USBC0_CTRL_MASK (0x3 << 8)
#define CCM_CCGR1_PIT_CTRL_MASK (0x3 << 14)
#define CCM_CCGR1_TCON0_CTRL_MASK (0x3 << 26)
#define CCM_CCGR1_WDOGA5_CTRL_MASK (0x3 << 28)
@@ -223,6 +225,8 @@ struct anadig_reg {
#define CCM_CCGR4_GPC_CTRL_MASK (0x3 << 24)
#define CCM_CCGR4_I2C0_CTRL_MASK (0x3 << 12)
#define CCM_CCGR6_OCOTP_CTRL_MASK (0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK (0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK (0x3 << 26)
#define CCM_CCGR6_DDRMC_CTRL_MASK (0x3 << 28)
#define CCM_CCGR7_SDHC1_CTRL_MASK (0x3 << 4)
#define CCM_CCGR7_USBC1_CTRL_MASK (0x3 << 8)