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authorFrancesco Dolcini <francesco.dolcini@toradex.com>2021-08-20 18:26:57 +0200
committerFrancesco Dolcini <francesco.dolcini@toradex.com>2021-08-20 18:26:57 +0200
commit240223cd41a776d1ddba96ac7252aeb4b2ebdb90 (patch)
treec32da1f1ca5aa238799e8bd8dfac7ceac6dbceb8
parent1ae3ca27d9f522fea084ee546f9a45157438e265 (diff)
colibri-imx6: use dynamic DDR calibration
Enable dynamic DDR calibration to have a reliable behavior on edge temperatures conditions. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
-rw-r--r--board/toradex/colibri_imx6/colibri_imx6.c22
-rw-r--r--configs/colibri_imx6_defconfig5
-rw-r--r--configs/colibri_imx6_tezi_defconfig1
3 files changed, 24 insertions, 4 deletions
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index f77a8a5b62..cfb61fa848 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -997,9 +997,28 @@ static void ddr_init(int *table, int size)
writel(table[2 * i + 1], table[2 * i]);
}
+/* Perform DDR DRAM calibration */
+static void spl_dram_perform_cal(u8 dsize)
+{
+#ifdef CONFIG_MX6_DDRCAL
+ int err;
+ struct mx6_ddr_sysinfo ddr_sysinfo = {
+ .dsize = dsize,
+ };
+
+ err = mmdc_do_write_level_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from write level calibration\n", err);
+ err = mmdc_do_dqs_calibration(&ddr_sysinfo);
+ if (err)
+ printf("error %d from dqs calibration\n", err);
+#endif
+}
+
static void spl_dram_init(void)
{
int minc, maxc;
+ u8 dsize = 2;
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL:
@@ -1009,6 +1028,7 @@ static void spl_dram_init(void)
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
@@ -1020,11 +1040,13 @@ static void spl_dram_init(void)
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
+ dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
};
udelay(100);
+ spl_dram_perform_cal(dsize);
}
static iomux_v3_cfg_t const gpio_reset_pad[] = {
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 310349aa7e..38c410b8a7 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00908000
@@ -19,7 +20,6 @@ CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg,MX6DL"
CONFIG_BOOTDELAY=1
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y
CONFIG_VERSION_VARIABLE=y
@@ -52,7 +52,6 @@ CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_NFS is not set
-CONFIG_CMD_BMP=y
CONFIG_CMD_BOOTCOUNT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
@@ -97,8 +96,6 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_HOST_ETHER=y
-# CONFIG_VIDEO_BPP8 is not set
-# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/colibri_imx6_tezi_defconfig b/configs/colibri_imx6_tezi_defconfig
index 78af054208..941be47f8b 100644
--- a/configs/colibri_imx6_tezi_defconfig
+++ b/configs/colibri_imx6_tezi_defconfig
@@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
+CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_DM_GPIO=y
# CONFIG_TDX_CFG_BLOCK_USB_GADGET_PID is not set