diff options
| author | Ye Li <ye.li@nxp.com> | 2021-07-29 20:15:20 -0700 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2021-07-29 23:25:51 -0700 |
| commit | f934f19accfe9cd17c0788ef35b7d22b57bcf10f (patch) | |
| tree | ae593a6f1ade456d3917b5c56372f331a949d060 | |
| parent | 5c630261528256ad1de61db154f6eec4596a3a62 (diff) | |
MLK-25349 imx8mq_evk: Enable PCIE VREG for 3.3v PHY supply
The bit12 of IOMUXC_GPR_GPR14/16 are used to bypass internal regulator for
two PCIE PHYs:
When PCIE_VPH = 3.3V, enable internal 3.3V to 1.8V regulator to generate the
1.8V, the register of IOMUXC_GPR_GPR14/16 bit 12 = 1'b0;
When PCIE_VPH = 1.8V, disable the internal 3.3V to 1.8V regulator, using the
external 1.8V for the PHY, the register of IOMUXC_GPR_GPR14/16 bit 12 = 1'b1;"
This bit is reset to 1 which means bypass the internal regulator. However the
EVK board connects 3.3v supply to PCIE_VPH. So we must enable the regulator,
otherwise it could potentially impact the product lifetime of the device.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Richard Zhu <hongxing.zhu@nxp.com>
(cherry picked from commit 3fd0991551c8236319b8bf29ca47813c9242c18f)
| -rw-r--r-- | board/freescale/imx8mq_evk/spl.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index bb8211dd7c..120810a111 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -218,6 +218,21 @@ int board_fit_config_name_match(const char *name) } #endif +#define GPR_PCIE_VREG_BYPASS BIT(12) +static void enable_pcie_vreg(bool enable) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + if (!enable) { + setbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS); + setbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS); + } else { + clrbits_le32(&gpr->gpr[14], GPR_PCIE_VREG_BYPASS); + clrbits_le32(&gpr->gpr[16], GPR_PCIE_VREG_BYPASS); + } +} + void board_init_f(ulong dummy) { int ret; @@ -225,6 +240,9 @@ void board_init_f(ulong dummy) /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + /* PCIE_VPH connects to 3.3v on EVK, enable VREG to generate 1.8V to PHY */ + enable_pcie_vreg(true); + arch_cpu_init(); init_uart_clk(0); |