diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2017-03-10 18:09:48 -0800 |
|---|---|---|
| committer | Marcel Ziswiler <marcel.ziswiler@toradex.com> | 2017-03-30 10:09:41 +0200 |
| commit | f0d5faf6f5ce11423bb26ee905ca22522cb62366 (patch) | |
| tree | 123cdf42a622a168cdd1ff057f0e138e0956e58c /arch/arm/cpu/armv7/mx6/soc.c | |
| parent | 0c62005b96efc9517ba450c4e788e5d4623fb6f5 (diff) | |
imx: imx-common: add elf firmware support
Support elf firmware files for the auxiliary Cortex-M4 core. This
has the advantage that the user does not need to know to which
address the binary has been linked to. However, in order to load
the elf sections to the right address, we need to translate the
Cortex-M4 core memory addresses to primary/host CPU memory
addresses (U-Boot is typically running on the A7/A9 core). This
allows to boot firmwares from any location with just using
bootaux, e.g.:
tftp ${loadaddr} low_power_demo.elf && bootaux ${loadaddr}
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Diffstat (limited to 'arch/arm/cpu/armv7/mx6/soc.c')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/soc.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 7231b569cd..0795c0a43e 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -645,6 +645,18 @@ void imx_setup_hdmi(void) #endif #ifdef CONFIG_IMX_BOOTAUX +#ifdef CONFIG_MX6SX +const struct memorymap hostmap[] = { + { .auxcore = 0x00000000, .host = 0x007f8000, .size = 0x8000 }, + { .auxcore = 0x1fff8000, .host = 0x007f8000, .size = 0x8000 }, + { .auxcore = 0x20000000, .host = 0x00800000, .size = 0x8000 }, + { .auxcore = 0x00900000, .host = 0x00900000, .size = 0x20000 }, + { .auxcore = 0x20900000, .host = 0x00900000, .size = 0x20000 }, + { .auxcore = 0x10000000, .host = 0x80000000, .size = 0x0fff0000 }, + { .auxcore = 0x80000000, .host = 0x80000000, .size = 0xe0000000 }, + { /* sentinel */ } +#endif + /* * Per the cortex-M reference manual, the reset vector of M4 needs * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses |